NIC Interrupt Control for Missed Events During Masked Periods

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Solution Overview

Problem

Network integrated circuits (NICs) are unable to transmit additional interrupt events during an interrupt disable period, causing additional packets to miss the opportunity for processing by the system end.

Innovation Solution

An interrupt control device with an interrupt request register and an interrupt mask register that records and outputs interrupt events during both enable and disable periods, allowing for the recording of additional events during disable periods and their output during enable periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the interrupt mask register disables interrupts during the interrupt disable period, then the system end can process interrupt events without interruption, but additional interrupt events cannot be recorded or output

Engineering Contradiction:

Improveinterrupt processing reliabilityVSAvoidinterrupt event loss

Core Design Contradiction:

ReliabilityVSLoss of information

Solution Approach 1:

The interrupt request register continuously monitors and records interrupt events even during the interrupt disable period, preparing the data in advance. When the interrupt enable period resumes, the pre-recorded interrupt events are then output, ensuring no interrupt information is lost while maintaining reliable interrupt processing during the disable period.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the interrupt control device continuously outputs interrupt events, then all packets can be notified for processing, but the system end cannot process interrupt events without interruption

Engineering Contradiction:

Improvepacket processing throughputVSAvoidinterrupt processing stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The interrupt control device operates in periodic cycles, alternating between interrupt enable periods and interrupt disable periods. During enable periods, interrupt events are output to the system end; during disable periods, the system end processes these events without interruption. This periodic switching ensures both complete packet notification and stable interrupt processing.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS20260072728A1Interrupt control device, interrupt control method, and network integrated circuit

Publication Date: 2026.03.12 REALTEK SEMICON CORP

AI summary

An interrupt control device includes an interrupt request register and an interrupt mask register. The interrupt request register is configured to record a first interrupt event during an interrupt enable period, and the interrupt control device outputs the first interrupt event during the interrupt enable period. The interrupt mask register is configured to switch the interrupt enable period to an interrupt disable period according to an interrupt acknowledge signal, and the interrupt request register records a second interrupt event during the interrupt disable period. The interrupt mask register is configured to switch the interrupt disable period to the interrupt enable period according to an end of interrupt signal, and the interrupt control device outputs the second interrupt event during the interrupt enable period.