NIC Master Timer for CPU Timestamp Alignment
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Solution Overview
Problem
Existing technologies face challenges in synchronizing time stamp counters (TSCs) across multiple CPU nodes to a common network reference, which is crucial for distributed applications that rely on network or global time.
Innovation Solution
Implementing a common master timer in a network interface controller (NIC) that can be calibrated using the network domain, allowing the NIC master timer to be synchronized to various network sources, and using this common reference to align TSCs across multiple CPU nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a common master timer is implemented in the NIC to synchronize TSCs across multiple CPU nodes, then time synchronization precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces a common master timer in the NIC as an intermediary device to synchronize TSCs across multiple CPU nodes. The master timer receives timing information from network sources (GPS, synchronous Ethernet, or IEEE 1588) and distributes synchronized time references to all CPU nodes, eliminating the need for direct peer-to-peer synchronization between nodes and achieving 100 ns or better alignment accuracy
Solution Approach 2:
The common master timer in the NIC serves multiple functions: it acts as a central time reference for all CPU nodes, provides calibration data for TSC alignment, and supports multiple network timing sources (GPS, synchronous Ethernet, IEEE 1588). This multi-functional design consolidates what would otherwise require separate synchronization mechanisms for each CPU node
2Reliability
If TSCs are aligned to a common network reference with high precision, then distributed application reliability is improved, but the difficulty of detecting and measuring timing relationships increases
Solution Approach 1:
The system implements feedback mechanisms where the NIC continuously monitors timing relationships between the master timer and individual CPU node TSCs. Calibration data is generated based on measured offsets and drift rates, and this feedback is used to adjust and maintain synchronization accuracy. The system can detect and correct timing deviations in real-time to maintain 100 ns alignment precision
Solution Approach 2:
The common master timer acts as an intermediary that simplifies the measurement and detection of timing relationships. Instead of requiring direct measurement between all pairs of CPU nodes (which would be complex), the master timer provides a central reference point that all nodes can measure against, reducing the measurement complexity from O(n²) to O(n)
Data Source
AI summary
Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.