Network Interface Card Memory Allocator for Reduced Read Latency

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Solution Overview

Problem

Existing memory allocation methods for data packets in network interface cards result in increased read latency due to non-continuous allocation of memory cells, as the control cell needs to be fetched before data cells, which complicates address management.

Innovation Solution

A memory allocator system that assigns contiguous memory space using a plurality of sub-allocators organized in decreasing size, allowing for continuous allocation of memory cells and eliminating the need for address storage in control cells, thereby reducing fetch latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory cells are allocated non-continuously for data packets, then memory allocation flexibility is improved, but read latency increases due to control cell fetch requirements

Engineering Contradiction:
Improvememory allocation flexibilityVSAvoidread latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The memory allocator is divided into multiple sub-allocators, each responsible for a specific segment of the memory space. This segmentation allows independent management of continuous and non-continuous allocation regions, enabling flexible allocation while maintaining continuous address spaces for time-critical operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different allocation strategies are applied to different memory regions. The first sub-allocator manages memory with continuous allocation semantics optimized for low latency, while the second sub-allocator handles non-continuous allocation for flexibility. Each region has tailored allocation properties matching its performance requirements.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If control cells store addresses for data cells, then non-continuous allocation is enabled, but fetch latency increases due to sequential access requirements

Engineering Contradiction:
Improveallocation pattern flexibilityVSAvoidfetch speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The address management function is extracted from the control cell and handled separately by the memory allocator subsystem. The control cell no longer needs to embed data cell addresses, allowing simplified control cell structure while the allocator independently tracks and manages address mappings for non-continuous allocations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory allocator acts as an intermediary between the control cell and data cells. It maintains separate address mapping information and resolves addresses without requiring them to be stored in the control cell, thereby eliminating the sequential fetch dependency while supporting flexible allocation patterns.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple sub-allocators are used for memory management, then allocation efficiency is improved, but system complexity increases

Engineering Contradiction:
Improvememory allocation efficiencyVSAvoidallocator structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The allocator is segmented into specialized sub-allocators with distinct responsibilities. This segmentation improves efficiency by allowing each sub-allocator to optimize its internal structure for its specific function (continuous vs. non-continuous allocation), while the overall system complexity is managed through clear separation of concerns and modular design.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240111667A1High Performance Memory Allocator
Publication Date: 2024.04.04 GOOGLE LLC
  • US20240111667A1 patent drawing
  • US20240111667A1 patent drawing
  • US20240111667A1 patent drawing

AI summary

Aspects of the disclosure are directed to a memory allocator for assigning contiguous memory space for data packets in on-chip memory of a network interface card. The memory allocator includes a plurality of sub-allocators that correspond to a structure of entries, where each entry represents a quanta of memory allocation. The sub-allocators are organized in decreasing size in the memory allocator based on the amount of memory quanta they can allocate.