NIC Multi-Stream Scheduling With DMA Timing Descriptors
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Solution Overview
Problem
Current network interface cards (NICs) are unable to efficiently schedule multiple data streams belonging to the same traffic class, leading to software-induced latency and jitter, which is undesirable for hard real-time applications.
Innovation Solution
Enhanced NIC architecture with dedicated DMA channels and prefetch cache for each data stream, using modified descriptors with parameters like launch time offset, gating cycle number, and reduction ratio for fine-grained scheduling control, eliminating software overhead and improving latency and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current NIC architecture schedules multiple data streams, then data transmission capability is provided, but software overhead causes latency and jitter
Solution Approach 1:
The patent extracts the scheduling function from software to hardware by implementing dedicated DMA channels and scheduling logic within the NIC. Each data stream has its own DMA channel that independently schedules packets, eliminating software involvement in the scheduling process and thereby removing software overhead that causes latency and jitter.
Solution Approach 2:
The NIC performs self-scheduling by using internal DMA channels that autonomously manage packet transmission for each data stream. The scheduling decision is made within the hardware itself based on descriptors and timing information, without requiring CPU intervention or software processing, enabling the system to serve itself.
2Measurement precision
If dedicated DMA channels are added for each data stream, then scheduling precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the NIC scheduling function into separate dedicated DMA channels, with each channel responsible for a specific data stream. This segmentation allows independent scheduling of multiple streams with precise timing control while keeping each individual channel's logic simple and manageable.
Solution Approach 2:
Each dedicated DMA channel is designed as a universal module that can handle any data stream by configuring its descriptor and timing parameters. This multi-functionality approach allows precise scheduling for different streams using the same hardware infrastructure, improving precision without proportionally increasing complexity.
3Productivity
If multiple data streams are scheduled by software, then flexibility is maintained, but processing time increases
Solution Approach 1:
The patent implements preliminary action by having the application program pre-configure descriptors with timing information, launch times, and scheduling parameters before data transmission begins. The DMA channels then execute these pre-planned schedules autonomously, reducing real-time processing time while maintaining flexibility through configurable descriptors.
Solution Approach 2:
The scheduling system maintains dynamics through configurable descriptors that can be dynamically adjusted for different data streams. Each DMA channel can be programmed with different timing parameters, reduction ratios, and launch times, allowing the system to adapt to varying traffic patterns without increasing processing time.
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AI summary
A network interface device for implementing multi-stream scheduling for time sensitive networking includes direct memory access (DMA) circuitry, comprising: descriptor parsing circuitry to read a packet descriptor from a descriptor cache, wherein the packet descriptor includes at least one scheduling control parameter including: a launch time offset, a gate cycle offset, or a reduction ratio; wherein the packet descriptor is associated with a packet stream having a traffic class; and scheduling circuitry to schedule packets from the packet stream for transmission using the at least one scheduling control parameter.