NIC Packet Switching Bypassing CPU Bottleneck
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Solution Overview
Problem
In conventional server systems with multiple network interface cards (NICs), network packets needing to be transferred between NICs are typically processed by the central processing unit (CPU), leading to reduced throughput and increased latency, especially as network traffic increases.
Innovation Solution
Implementing a method where a first NIC receives a network packet, identifies the destination NIC, places the packet in host memory without using the CPU resources, notifies the second NIC, and allows it to retrieve and transmit the packet, thereby bypassing the host processor for packet switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If network packets are processed by the CPU in conventional server systems, then packet switching between NICs can be achieved, but network throughput decreases and latency increases
Solution Approach 1:
The patent extracts the packet switching function from the CPU and relocates it to the NICs themselves. The NICs are equipped with switching logic that can independently determine destination NICs and forward packets without CPU intervention, thereby eliminating the CPU as a bottleneck in the packet switching path and improving network throughput while reducing latency.
Solution Approach 2:
The NICs are designed to perform packet switching autonomously using their own resources (buffers, switching logic, and memory). Each NIC can receive packets, determine the destination NIC, and forward packets without requiring CPU processing, enabling the network interface cards to serve themselves in the packet switching function.
2Productivity
If the CPU processes packets for switching between NICs, then packet delivery is achieved, but processor utilization is reduced
Solution Approach 1:
The packet switching function is extracted from the CPU and assigned to the NICs. The NICs contain dedicated switching logic and buffers that enable them to handle packet forwarding independently, freeing the CPU from this task and allowing it to be utilized for more computationally intensive workloads, thereby improving overall system efficiency.
Solution Approach 2:
The patent introduces an intermediary switching mechanism within the NIC that mediates packet transfer between NICs without involving the CPU. This intermediary switching logic acts as a bridge, enabling direct packet routing between network interfaces while the CPU remains idle or engaged in other tasks.
Data Source
AI summary
Methods and systems for network communication are provided. One method includes, receiving a network packet at a first network interface card (NIC) operationally coupled to a computing device; identifying a second NIC as a destination for the network packet; placing the network packet by the first NIC at a host memory location, without utilizing resources of a processor of the computing device; notifying the second NIC that the network packet has been placed at the host memory location; retrieving the network packet by the second NIC from the host memory location; transmitting the network packet by the second NIC to another destination; notifying the first NIC by the second NIC that the packet has been transmitted by the second NIC; and freeing the host memory location by the first NIC.