NIC Packet Timestamping Bandwidth Optimization
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Solution Overview
Problem
Current edge computing networks face challenges in achieving high bandwidth for packet timestamping due to bottlenecks in existing Network Interface Controller (NIC) designs, particularly at higher line rates, which result in reduced effective transmit bandwidth and increased silicon area requirements, making them unsuitable for edge computing applications with stringent latency and power constraints.
Innovation Solution
The proposed solution decouples the operation of writing payload timestamps and status to shared memory from releasing descriptors, using a writeback address pointer to store timestamps and status separately, allowing for faster descriptor overwrite and reducing the descriptor cache size, thereby improving bandwidth utilization and reducing silicon area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing NIC designs are used for packet timestamping, then timestamping functionality is provided, but bandwidth is reduced and silicon area increases at higher line rates
Solution Approach 1:
The patent segments the descriptor structure into separate components: the original descriptor and a new writeback address pointer. This segmentation allows the timestamping operation to write to a separate location rather than requiring the full descriptor to be held in cache, thereby reducing descriptor cache size and silicon area while maintaining bandwidth utilization.
Solution Approach 2:
The patent introduces a writeback address pointer as an intermediary element. This pointer serves as a mediator between the timestamping operation and the shared memory, allowing timestamps to be written to separate locations without blocking descriptor release. This intermediary mechanism reduces the bandwidth bottleneck and silicon area requirements.
2Measurement precision
If descriptors are held in cache for timestamping completion, then timestamp accuracy is maintained, but descriptor cache size increases and bandwidth is reduced
Solution Approach 1:
The patent implements preliminary action by having the NIC write the writeback address pointer to the descriptor cache before the timestamping operation completes. This allows the main processor to retrieve the pointer and access the timestamp from shared memory without requiring the descriptor to remain cached, thereby maintaining timestamp accuracy while freeing up descriptor cache space and improving bandwidth.
Solution Approach 2:
The patent uses copying by creating a writeback address pointer that references the timestamp location in shared memory. Instead of keeping the actual timestamp data in the descriptor cache, the system copies the address information and allows the main processor to retrieve the timestamp from its original location in shared memory, reducing cache requirements while maintaining data integrity.
3Area of stationary object
If descriptor cache size is reduced, then silicon area is reduced, but bandwidth utilization decreases
Solution Approach 1:
The patent transitions from a two-dimensional descriptor cache structure to a three-dimensional memory hierarchy by introducing shared memory as an additional storage dimension. The writeback address pointer enables access to timestamps in shared memory, effectively adding another layer of storage that compensates for the reduced descriptor cache size and maintains bandwidth utilization.
Data Source
AI summary
Methods, apparatus, systems, and articles of manufacture are disclosed to improve bandwidth for packet timestamping. An example apparatus includes cache to store a pointer, the pointer indicative of an address in shared memory where a timestamp is to be stored, the pointer corresponding to a descriptor of data to be transmitted to a second device. The example apparatus also includes memory access control circuitry to parse the descriptor to determine the pointer and cause storage of the pointer in the cache. Additionally, the memory access control circuitry of the example apparatus is to set a control bit of the descriptor to indicate that the descriptor may be overwritten.