Network Interface Card Parallel Instruction Processing

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Solution Overview

Problem

Conventional data processing methods in RDMA technology face inefficiencies due to out-of-order segment processing, leading to reduced data transmission speed and increased processing delays, particularly when the length of the SQE is less than or equal to a preset threshold, resulting in wasted PCIe bandwidth and processor load inefficiencies.

Innovation Solution

The method offloads the order-preserving operation of instruction segments to the network interface card, allowing the processor to deliver segments in parallel without focusing on order preservation, utilizing PCIe barriers to ensure correct sequencing and reducing the number of packets between the processor and network interface card, thereby improving PCIe bandwidth utilization and reducing processing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the processor sends instruction segments to the network interface card in parallel without order preservation, then data transmission speed is improved and PCIe bandwidth utilization is enhanced, but out-of-order processing problems occur at the network interface card

Engineering Contradiction:
Improvedata transmission speedVSAvoidinstruction segment ordering
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The instruction segment is divided into multiple packets for parallel transmission. Each packet contains a sequence number to enable the network interface card to reassemble them in the correct order, thus achieving both high-speed parallel transmission and reliable ordering.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary buffer and sequence number mechanism between the processor and network interface card. The processor sends packets in parallel with sequence numbers, and the network interface card uses the sequence numbers to reorder packets correctly, resolving the ordering problem without blocking parallel transmission.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the processor uses PCIe barrier instructions to ensure order preservation, then instruction segment ordering is maintained, but PCIe bandwidth is wasted and processing delay increases

Engineering Contradiction:
Improveinstruction segment orderingVSAvoidprocessing delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the order preservation function from the processor's transmission process and relocates it to the network interface card. The processor only needs to send packets with sequence numbers in parallel, while the network interface card handles the reordering using the extracted sequence number information, eliminating the need for PCIe barrier instructions and reducing processing delay.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If the processor handles order preservation serially by waiting for each segment to be sent before clearing the buffer, then correct sequencing is achieved, but data processing efficiency is reduced

Engineering Contradiction:
Improvedata sequencingVSAvoiddata processing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The network interface card performs self-service by autonomously handling the reordering of instruction segments using sequence numbers embedded in each packet. This eliminates the need for the processor to serially manage buffer clearing and order preservation, allowing the processor to continue sending packets in parallel and significantly improving data processing efficiency.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3907946B1Data processing method, network card, and server
Publication Date: 2024.11.27 HUAWEI TECH CO LTD
  • EP3907946B1 patent drawingFigure 1
  • EP3907946B1 patent drawingFigure 2
  • EP3907946B1 patent drawingFigure 3

AI summary

This application discloses a data processing method, a network interface card, and a server. The method includes: After receiving an ith PCIe packet, a network interface card stores a jth instruction segment in a jth storage unit that is in a first storage area. When all n instruction segments of the first SQE are stored in the first storage area, the network interface card obtains a first SQE, an identifier of a queue pair QP to which the first SQE belongs, and a location identifier of the first SQE in the QP according to the instructions in n storage units in the first storage area; the network interface card performs data processing based on to the identifier of the QP to which the first SQE belongs and the location identifier of the first SQE in the QP. This resolves a problem, of low processing efficiency and a high delay, caused in a conventional SQE order preserving processing process.