Programmable NIC Pipeline Integrates Accelerator to Reduce PCIe Traffic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Data movement between a host, an accelerator, and a network incurs significant overhead due to bus bottlenecks, particularly in virtualized environments where packet classification and parsing tasks increase power consumption and memory requirements, making existing 'bump-in-the-wire' architectures impractical.
Innovation Solution
A network node architecture that integrates a hierarchical packet processing pipeline within a NIC, allowing the accelerator to focus on specific acceleration tasks while the NIC handles packet parsing and other operations, reducing PCIe traffic and host overhead by minimizing data traversal through the PCIe bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted through the PCIe bus between host, accelerator, and network, then data movement is enabled, but bus bottleneck and overhead increase
Solution Approach 1:
The patent merges the network interface controller and accelerator into a single integrated device, allowing data to be processed and accelerated without leaving the device. This eliminates the need for data to traverse the PCIe bus multiple times between separate host, accelerator, and network components, thereby reducing bus bottleneck overhead and processing latency while maintaining high data throughput.
2Productivity
If accelerator performs packet classification and parsing, then acceleration capability is provided, but power consumption and memory requirements increase
Solution Approach 1:
The patent segments the packet processing functions by having the NIC handle packet classification, parsing, and routing decisions, while the accelerator focuses only on the computationally intensive acceleration tasks. This division allows the accelerator to be smaller and consume less power, as it does not need to perform resource-intensive packet classification and parsing operations.
Solution Approach 2:
The NIC acts as an intermediary between the network and accelerator, pre-processing packets and preparing them for acceleration. By filtering and preparing data before it reaches the accelerator, the NIC reduces the workload on the accelerator, enabling smaller, lower-power acceleration hardware to achieve the same effective throughput.
3Adaptability or versatility
If data traverses PCIe bus multiple times, then data can be processed by multiple components, but overhead and latency increase
Solution Approach 1:
The patent combines multiple processing functions within a single integrated device, allowing data to be processed by multiple functional units (NIC and accelerator) without physically leaving the device. This maintains processing flexibility and adaptability while eliminating the need for repeated PCIe bus traversals that would increase data movement time and overhead.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A network interface controller (30) that is connected to a host (34) and a packet communications network. The network interface controller (30) includes electrical circuitry configured as a packet processing pipeline (72) with a plurality of stages (76, 78, 80, 82). It is determined in the network interface controller (30) that at least a portion of the stages (76, 78, 80, 82) of the pipeline (72) are acceleration-defined stages (78, 80). Packets are processed in the pipeline (72) by transmitting data to an accelerator (74) from the acceleration-defined stages (78, 80), performing re- spective acceleration tasks (86, 90) on the transmitted data in the accelerator (74), and returning processed data from the accelerator (74) to receiving stages (80, 82) of the pipeline (72).