NIC Packet Scheduling and DMA for Deterministic TSN Latency
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Solution Overview
Problem
Network interface controllers (NICs) face design limitations that lead to latency, jitter, and transmission delays due to inefficient packet scheduling and direct memory access (DMA) operations, particularly in time-sensitive networking applications, where existing scheduling algorithms fail to address the head of the line blocking problem and lack of traffic class quality of service differentiation.
Innovation Solution
Implementing traffic-class-based scheduling and decoupled descriptor DMA, where separate I/O interfaces and request queues are used for different traffic classes, and descriptor prefetching is decoupled from packet data fetching, utilizing separate DMA engines for each, to ensure deterministic and low-latency packet transmissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional packet scheduling and DMA operations are used in NIC, then device complexity is reduced, but latency and jitter increase leading to packet transmission delays
Solution Approach 1:
The patent segments the scheduling and DMA operations into separate functional units within the NIC. The packet scheduler is divided into traffic class schedulers that independently manage different traffic classes, while DMA operations are separated into descriptor DMA and data DMA engines. This segmentation allows parallel processing of scheduling decisions and memory access operations, reducing packet transmission latency without requiring excessive overall system complexity.
Solution Approach 2:
The patent introduces a new dimension of operation by implementing separate I/O interfaces for different traffic classes (e.g., express and normal traffic). This dimensional separation allows high-priority packets to traverse a dedicated path independent of standard traffic flows, effectively adding a temporal and spatial dimension to packet handling that reduces latency for time-sensitive applications.
2Reliability
If separate I/O interfaces and request queues are implemented for different traffic classes, then determinism and latency are improved, but device complexity increases
Solution Approach 1:
The NIC architecture is segmented into distinct traffic class handlers, each with dedicated request queues and I/O interfaces. This segmentation enables deterministic handling of high-priority traffic independent of lower-priority traffic, improving reliability for time-sensitive applications while maintaining manageable complexity through modular design.
Solution Approach 2:
Different I/O interfaces and request queues are assigned specific quality characteristics tailored to their traffic class. Express traffic receives high-priority interfaces with guaranteed service, while normal traffic uses standard interfaces. This local quality differentiation ensures deterministic transmission for critical packets without requiring the entire system to operate at maximum complexity.
3Loss of time
If descriptor prefetching is decoupled from packet data fetching using separate DMA engines, then end-to-end latency is reduced, but device complexity increases
Solution Approach 1:
The DMA functionality is segmented into separate descriptor DMA engines and data DMA engines. The descriptor DMA engine independently prefetches packet metadata from memory, while the data DMA engine handles actual packet payload transfers. This segmentation eliminates the sequential dependency where data DMA had to wait for descriptor DMA completion, significantly reducing end-to-end latency through parallel operation.
Solution Approach 2:
The descriptor DMA engine performs preliminary action by prefetching packet descriptors and metadata before the data DMA engine needs to access them. This preliminary action allows the data DMA engine to immediately begin packet payload transfers without waiting for descriptor processing, reducing overall transmission latency through advance preparation.
Data Source
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AI summary
In one embodiment, a network interface controller (NIC) includes multiple packet transmission queues to queue data packets for transmission. The data packets are assigned to multiple traffic classes. The NIC also includes multiple input/output (I/O) interfaces for retrieving the data packets from memory. Each I/O interface is assigned to a subset of the traffic classes. The NIC also includes scheduler circuitry to select a first data packet to be retrieved from memory, and direct memory access (DMA) engine circuitry to retrieve the first data packet from memory via one of the I/O interfaces based on the traffic class of the first data packet, and store the first data packet in one of the packet transmission queues. The NIC also includes a transmission interface to transmit the first data packet over a network at a corresponding launch time indicated by the scheduler circuitry.