NIC Sideband Retimer With Delayed Clock for Long RMII Links
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Solution Overview
Problem
Propagation delay in communication between a baseboard management controller (BMC) and a network interface card (NIC) due to long cabling affects data validity, particularly in computing devices with extended pathways.
Innovation Solution
A network controller sideband interface retimer apparatus that includes a second clock circuit to transmit a separate clock signal to the NIC, a NIC data relay circuit to receive and transmit data packets, and a clock delay circuit to adjust the clock signal to coincide with data validity, using hardware and programmable hardware devices or executable code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If long cabling is used between BMC and NIC, then physical distance requirements are met, but propagation delay affects data validity
Solution Approach 1:
The patent applies preliminary action by introducing a retimer device that pre-adjusts and retimes clock signals before they reach the NIC through long cables. The retimer compensates for propagation delays in advance by measuring and adjusting clock timing, ensuring data validity is maintained despite the extended cable length between BMC and NIC.
2Reliability
If clock signal is synchronized with data receipt, then data validity is maintained, but propagation delay must be compensated
Solution Approach 1:
The patent applies parameter changes by modifying the clock signal parameters (timing, phase, frequency) through the retimer device. The retimer adjusts the clock signal's timing characteristics to compensate for propagation delays, changing the clock parameter so that it synchronizes with data receipt after accounting for the cable's propagation delay, thereby maintaining data validity.
3Reliability
If separate clock signal is transmitted to NIC, then clock synchronization is improved, but device complexity increases
Solution Approach 1:
The patent applies the intermediary principle by introducing a retimer device as a mediator between the BMC clock signal and the NIC. This retimer acts as an intermediate component that receives the clock signal from the BMC, adjusts and retimes it, then transmits the corrected clock signal to the NIC. This intermediary approach improves clock synchronization reliability while containing the complexity within a dedicated retimer module rather than distributing it throughout the entire system.
Data Source
AI summary
An apparatus with a network controller sideband interface retimer includes a second clock circuit configured to transmit a second clock signal to a NIC. The second clock signal is separate from a first clock signal from a clock connected to a BMC. The apparatus includes a NIC data relay circuit configured to receive data packets from the NIC on a first reduced media independent interface (“RMII”) bus and to transmit the received data packets to the BMC over a second RMII bus. The apparatus includes a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal. The delay is adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid.