Network Interface Controller Virtual Address Translation Latency
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Solution Overview
Problem
High-performance server networks using virtual machines experience latency due to the need for virtual I/O address translation, which negatively affects network performance when network interface devices initiate memory transactions with untranslated guest bus addresses.
Innovation Solution
Implementing directed I/O support technology in network interface controllers to monitor and translate virtual 'guest' bus addresses at opportune times, reducing or eliminating latency by requesting translations only when necessary, and utilizing address translation caching for repeated addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the NIC initiates memory transactions with untranslated guest bus addresses, then the network interface device can operate with virtual machine addresses, but translation latency is incurred that negatively affects network performance
Solution Approach 1:
The NIC proactively requests address translations from the memory management unit before initiating memory transactions with guest bus addresses. By obtaining translations in advance and caching them, the system eliminates translation latency during actual data transfer operations, thus maintaining virtual address compatibility while removing the time penalty.
Solution Approach 2:
The system caches translated address mappings in the NIC for repeated use. When the same guest bus address needs to be accessed again, the cached translation is used immediately without requiring another translation request, significantly reducing repeated translation latency while maintaining adaptability to virtual addressing.
2Measurement precision
If address translations are requested for every memory transaction, then accurate physical address mapping is achieved, but translation requests incur latency that reduces network performance
Solution Approach 1:
The NIC monitors the transmit and receive rings to detect when descriptors are written, then selectively requests translations only when needed. This feedback mechanism ensures accurate address mapping is obtained precisely when required, while avoiding unnecessary translation requests that would reduce network throughput.
Solution Approach 2:
The system creates and maintains a cached copy of address translations in the NIC. This cached copy provides accurate physical address mappings for repeated accesses without requiring continuous communication with the memory management unit, thus preserving accuracy while maximizing network throughput.
3Loss of time
If the NIC monitors and translates guest bus addresses at opportune times, then translation latency is reduced or eliminated, but the complexity of address management increases
Solution Approach 1:
The NIC autonomously monitors its own transmit and receive rings, detects when descriptors are written, and independently manages the translation request process. By self-managing address translation without requiring external coordination, the system reduces translation latency while the modular design keeps the added complexity contained within the NIC's address management subsystem.
Data Source
AI summary
A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface controller to attempt to retrieve a translation for the guest bus address. The method includes using the network interface controller to read the descriptor from the transmit ring.