3D Memory Select Pattern With Nickel Silicide for Lower RC Delay
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor memory devices deteriorates as more memory cells are stacked, leading to increased RC delay and resistance in select transistors, which affects integration density and performance.
Innovation Solution
A semiconductor device with a stacked structure of conductive and insulating patterns, including a select pattern with a first and second conductive portion where the second conductive portion covers the sidewall and top surface of the first, and is made of nickel silicide, coupled with a select channel layer and capping pattern, to minimize RC delay and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells stacked on top of each other is increased to improve integration density, then integration density is improved, but operational reliability deteriorates due to increased RC delay and resistance
Solution Approach 1:
The patent changes the material parameter of the select transistor components from conventional materials to nickel silicide, which has superior electrical properties including lower resistance. This material substitution directly addresses the increased RC delay and resistance problems that occur when stacking more memory cells, thereby maintaining operational reliability while enabling higher integration density.
Solution Approach 2:
The patent employs composite material structures in the select transistor, specifically combining nickel silicide with other materials in a multi-layer configuration. The select transistor includes a gate electrode with nickel silicide, source/drain regions with nickel silicide, and associated conductive patterns, creating a composite structure that optimizes both electrical performance and structural integrity for high-density stacking.
2Quantity of substance
If more memory cells are stacked to increase integration density, then integration density is improved, but RC delay increases affecting performance
Solution Approach 1:
The patent modifies the electrical parameters of the select transistor by substituting conventional materials with nickel silicide, which exhibits lower resistivity. This parameter change in the material composition directly reduces the resistance component of RC delay, enabling faster signal transmission through the stacked memory structure and improving overall device performance.
Solution Approach 2:
The patent applies nickel silicide specifically to critical regions where RC delay has the most impact, such as the gate electrode and source/drain regions of the select transistor. This localized application of high-performance material optimizes the electrical characteristics at key interfaces and conductive paths without requiring uniform material substitution throughout the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes RC delay and reduces resistance in select transistors, enhancing the operational reliability and integration density of three-dimensional semiconductor memory devices.
Implementation Method 1
forming a diffusion metal layer covering the select channel layer and the preliminary select pattern, and diffusing metal of the diffusion metal layer into the select channel layer and the preliminary select pattern
Data Source
AI summary
A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.