Stress-Reduced Ni-P/Pd Wafer Coatings for Warpage Control
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Solution Overview
Problem
Existing wafer metallization processes result in high internal stress in Ni—P/Pd stacks, leading to warpage issues due to undesired tensile stress, which complicates wafer level miniaturization and electrical signal integrity.
Innovation Solution
A substrate with a bondable metallic coating comprising a Ni—P layer with 10.5 to 14 wt.% P content, a Pd layer, and optionally an Au layer, where the Ni—P layer thickness ranges from 0.2 to 10 μm, the Pd layer from 0.05 to 1.0 μm, and the Au layer from 0.01 to 0.5 μm, resulting in reduced internal stress not exceeding 34.48 MPa, thereby minimizing or avoiding warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Ni-P/Pd stacking processes are used, then metal stack reliability is achieved, but high internal tensile stress causes wafer warpage
Solution Approach 1:
The patent applies parameter changes by optimizing the phosphorus content in the Ni-P layer to a specific range (8-14 wt.%, preferably 10-12 wt.%) and controlling the thickness ratio between Ni-P and Pd layers. This changes the inherent stress characteristics of the electroless plating process, transforming the normally high-tensile-stress configuration into a low-stress or compressive-stress configuration, thereby resolving the contradiction between maintaining metal stack reliability and reducing internal tensile stress that causes wafer warpage
Solution Approach 2:
The patent employs composite materials by creating a multi-layer metal stack structure consisting of Ni-P layer, Pd layer, and optionally Au layer, where each layer has specific compositional and thickness characteristics. The Ni-P layer with controlled phosphorus content (8-14 wt.%) forms a composite structure with the Pd layer, where the Ni-P layer's compressive stress compensates for the Pd layer's tensile stress, achieving overall low internal stress while maintaining the reliability benefits of the composite metal stack
2Manufacturing precision
If wafer level miniaturization is pursued, then electrical signal integrity is improved, but wafer warpage from metal stack stress complicates the process
Solution Approach 1:
The patent applies parameter changes by precisely controlling the phosphorus content (8-14 wt.%) and thickness parameters of the Ni-P and Pd layers to achieve low internal stress, enabling wafer level miniaturization without warpage complications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress-reduced Ni—P/Pd stack minimizes warpage and ensures reliable metal stack integrity for wafer miniaturization and electrical signal integrity by maintaining compressive or low tensile stress within acceptable limits.
Implementation Method 1
followed by the plating of Ni—P and Pd (and optionally Au) on individual compartments of the wafer surface
Data Source
AI summary
The invention relates to a substrate having a bondable metal coating comprising, in this order, on an Al or Cu surface: (a) a Ni—P layer, (b) a Pd layer and, optionally, (c) an Au layer, wherein the thickness of the Ni—P layer (a) is 0.2 to 10 m, the thickness of the Pd layer (b) is 0.05 to 1.0 m and the thickness of the optional Au layer (c) is 0.01 to 0.5 m, and wherein the Ni—P layer (a) has a P content of 10.5 to 14 wt.-%. The deposit internal stress of the resulting Ni—P/Pd stack is not higher than 34.48M−Pa (5,000 psi). Further, a process for the preparation of such a substrate is described.