NiSi Metal Stack Backside Metallization Wafer Bow
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Solution Overview
Problem
The cost-intensive preparation of metal stacks on semiconductor substrates for electronic devices, particularly the BackSide Metallization (BSM), hinders cost reduction, reliability improvement, and minimization of wafer and chip bow due to material reactivity and thermal expansion differences.
Innovation Solution
A metal stack comprising a nickel silicon (NiSi) first layer, with nitrogen (N) impurities incorporated through magnetron sputtering, is used, which reacts slower with solder materials, allowing for thinner layers and reduced fabrication costs, and a barrier layer to prevent impurity diffusion, enhancing solder joint quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional metal stacks are used for BackSide Metallization, then soldering reliability is maintained, but fabrication costs increase and manufacturing time extends
Solution Approach 1:
The patent changes the chemical composition parameters of the metal stack by incorporating nitrogen impurities into the nickel layer and using specific metal alloys (Cu-Sn, Cu-Ni-Sn) with controlled concentrations. This parameter modification reduces the reactivity of the first metal layer with solder material, allowing for thinner layers and reduced fabrication costs while maintaining soldering reliability through the barrier layer design
Solution Approach 2:
The patent employs composite material structures in multiple layers: the first metal layer uses Cu-Sn or Cu-Ni-Sn alloys, the second metal layer uses Ni or Ni alloys, and the barrier layer uses WSi or MoSi compounds. These composite structures provide both cost reduction through optimized material selection and reliability through the specific functional properties of each material layer
2Productivity
If reactive metal layers are used in metal stacks, then electrical conductivity is improved, but wafer bow and chip bow increase
Solution Approach 1:
The patent modifies the composition parameters by adding nitrogen impurities to the nickel layer and using controlled alloy compositions with specific Sn and Ni concentrations. These parameter changes reduce the thermal reactivity of the metal layers, minimizing thermal expansion differences that cause wafer and chip bow while preserving electrical conductivity through the conductive alloy composition
Solution Approach 2:
The patent applies different material properties to different layers: the first metal layer (Cu-Sn or Cu-Ni-Sn) provides local electrical conductivity, the second metal layer (Ni or Ni alloy) provides structural stability and nitrogen incorporation for bow control, and the barrier layer (WSi or MoSi) provides localized protection against interdiffusion. This local quality differentiation resolves the contradiction between conductivity and flatness
3Reliability
If thicker metal layers are used to prevent impurity diffusion, then solder joint quality is improved, but fabrication costs and manufacturing time increase
Solution Approach 1:
The patent introduces a barrier layer composed of WSi or MoSi compounds as an intermediary between the metal layers and the semiconductor substrate. This barrier layer effectively prevents impurity diffusion and protects the solder joint quality, allowing the overlying metal layers to be thinner and reducing fabrication costs while maintaining the protective function
Solution Approach 2:
The patent changes the functional parameter of impurity diffusion prevention by using the barrier layer with specific WSi or MoSi composition rather than relying on increased metal layer thickness. This parameter change enables thinner metal layers to achieve the same protective effect, reducing material costs and manufacturing time while maintaining solder joint quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The NiSi layer reduces fabrication time and costs, minimizes wafer and chip bow, and improves solder joint reliability by controlling thermal expansion and preventing delamination, while maintaining performance.
Implementation Method 1
nitrogen (N) impurities incorporated through magnetron sputtering
Data Source
AI summary
An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.