NiSi-NiV Metallization Stack for Low-Warpage Semiconductor Bonding
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Solution Overview
Problem
Power semiconductor module arrangements face challenges in achieving reliable and corrosion-resistant connections between semiconductor devices and electrically conductive layers, while also requiring low production costs and high yield to minimize chip and wafer warpage.
Innovation Solution
A semiconductor device with a layer stack comprising a first layer of NiSi and a second layer of NiV, where the second layer is positioned between the first layer and the semiconductor wafer or chip, providing improved adhesion and reducing wafer warpage through controlled consumption during soldering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional metallization layer is used for mounting semiconductor devices, then the connection reliability is insufficient and prone to corrosion, but using advanced materials and layer structures increases production cost
Solution Approach 1:
The metallization layer is segmented into multiple functional layers: a first metallization layer (Ni) for mounting the semiconductor device, a second metallization layer (NiSi) formed by reaction with silicon, and a third metallization layer (NiV) for adhesion. This segmentation allows each layer to perform its specific function optimally, improving connection reliability while maintaining cost-effectiveness through controlled material usage.
Solution Approach 2:
The invention uses composite metallization structures combining different materials (Ni, NiSi, NiV) with complementary properties. The NiV layer provides adhesion, the NiSi layer provides corrosion resistance and controlled reaction, and the Ni layer provides electrical conductivity and mounting functionality. This composite approach achieves superior reliability without excessive cost increase.
2Productivity
If soldering techniques are used to mount semiconductor devices, then production speed is achieved, but chip and wafer warpage increases reducing yield
Solution Approach 1:
The invention changes the material parameters of the metallization layers, specifically using NiV with controlled vanadium content (1-10 at.%) to reduce thermal stress and warpage during soldering. The NiSi layer with controlled silicon content (1-10 at.%) also contributes to stress management. These parameter optimizations allow soldering to proceed at high speed while minimizing warpage-induced defects.
Solution Approach 2:
The NiV layer acts as an intermediary between the semiconductor device and the substrate, absorbing thermal expansion differences and reducing warpage during the soldering process. This mediator layer enables high-speed soldering without the warpage problems that would otherwise reduce manufacturing yield.
3Strength
If a single metallization layer is used, then device complexity is reduced, but connection strength and adhesion are insufficient
Solution Approach 1:
The metallization connection structure is segmented into three distinct layers with specific functions: the first Ni layer for electrical connection and mounting, the NiSi reaction layer for corrosion resistance, and the NiV adhesion layer for mechanical bonding. This segmentation provides superior connection strength while keeping each individual layer simple and well-defined.
Solution Approach 2:
Each metallization layer is optimized for its specific local function: Ni for conductivity and mounting, NiSi for corrosion resistance at the interface, and NiV for adhesion to the substrate. This local optimization of material properties achieves maximum connection strength without requiring excessive structural complexity throughout the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and mechanical stability of the connection, reducing wafer warpage and production costs by utilizing NiSi for a slower reaction rate and NiV for adhesion, maintaining a stable interface during thermomechanical stress.
Implementation Method 1
a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die
Implementation Method 2
NiV for adhesion, maintaining a stable interface during thermomechanical stress
Data Source
AI summary
A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.