NiSi-NiV Layer Stack for Reliable Semiconductor Solder Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power semiconductor module arrangements face challenges in achieving reliable and corrosion-resistant connections between semiconductor devices and electrically conductive layers, while also requiring low production costs and high yield to minimize chip and wafer warpage.
Innovation Solution
A semiconductor device with a layer stack comprising a first layer of NiSi and a second layer of NiV, where the second layer is positioned between the first layer and the semiconductor wafer or chip, providing improved adhesion and reducing wafer warpage through controlled consumption during soldering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single Ni layer is used for mounting the semiconductor device, then the structure is simple and production cost is low, but the connection reliability is insufficient and corrosion resistance is poor
Solution Approach 1:
The single Ni layer is segmented into two distinct layers: a first Ni layer (5-20 nm thick) that provides corrosion resistance and a second Ni layer (20-50 nm thick) that ensures mechanical strength and solderability. This segmentation allows each layer to perform its specific function optimally, improving overall connection reliability while maintaining a relatively simple structure.
Solution Approach 2:
The patent uses a composite Ni-Ni layer structure where two layers of the same material are deposited with different thicknesses and different functional requirements. The first layer acts as a protective barrier against corrosion, while the second layer provides the necessary mechanical properties for mounting, creating a composite structure that combines multiple functions.
2Productivity
If conventional mounting techniques are used, then production cost is low, but chip and wafer warpage occurs reducing yield
Solution Approach 1:
The patent changes the physical parameters of the mounting surface by depositing a specific thickness range of Ni layers (5-50 nm total). This parameter optimization reduces thermal expansion mismatch and stress during soldering, minimizing warpage and improving yield without requiring complex manufacturing processes.
Solution Approach 2:
The Ni layers are deposited in advance on the semiconductor device before mounting, creating a pre-prepared interface that facilitates reliable connection. This preliminary action of depositing the corrosion-resistant and mechanically-strong Ni layers before the mounting process prevents warpage and ensures high yield.
3Strength
If the Ni layer is made thicker to improve mechanical strength, then connection strength increases, but wafer warpage increases and production cost increases
Solution Approach 1:
Instead of using a single thick Ni layer that causes warpage, the patent segments the total thickness (20-50 nm) into two layers with different thicknesses. The first layer (5-20 nm) provides sufficient corrosion protection, while the second layer (20-50 nm) provides mechanical strength, achieving the desired connection strength without excessive total thickness that would cause warpage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and mechanical stability of the connection, reduces wafer warpage, and minimizes production costs by optimizing the layer structure and deposition techniques, ensuring high throughput and resistance to thermomechanical stress.
Implementation Method 1
A semiconductor device with a layer stack comprising a first layer of NiSi and a second layer of NiV, where the second layer is positioned between the first layer and the semiconductor wafer or chip, providing improved adhesion
Implementation Method 2
controlled consumption during soldering
Data Source
AI summary
A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.