Nitridated STI Hard Mask for Gate Replacement Nanostructures

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Solution Overview

Problem

The etching process in the gate replacement (RPG) step can damage the oxide material in shallow trench isolation (STI) regions, leading to dishing or voids, which degrade device performance and increase leakage current between metal gates in semiconductor devices.

Innovation Solution

The implementation of protection hard masks over the STI regions, formed by nitridating a dielectric layer using directional plasma or thermal nitridation processes, to shield the STI regions from etching damage during the RPG process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If etching process is performed in gate replacement step, then gate structure can be replaced, but oxide material in STI regions is damaged causing dishing or voids

Engineering Contradiction:
Improvegate replacement capabilityVSAvoidSTI region integrity
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

A protection hard mask layer is introduced as an intermediary between the etching process and the STI region oxide material. This hard mask layer selectively protects the STI region from etching damage while allowing the gate replacement process to proceed. The hard mask is formed over the STI region before etching and is removed after etching completes the gate replacement.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protection hard mask is applied in advance before the harmful etching process to prevent damage to the STI region. By establishing this protective layer beforehand, the oxide material in the STI region is shielded from the detrimental effects of the etching process that would otherwise cause dishing or voids.

Inventive Principle:
Principle #9Preliminary anti-action

2Adaptability or versatility

If etching process is performed in gate replacement step, then gate structure can be replaced, but leakage current between metal gates increases

Engineering Contradiction:
Improvegate replacement capabilityVSAvoidleakage current control
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The protection hard mask serves as a mediator that prevents direct contact between the etching process and the STI region oxide material. By blocking the etching damage, the hard mask prevents the formation of defects that would create leakage paths, thereby maintaining electrical isolation and reducing leakage current between metal gates.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Strength

If nitridation process is applied to dielectric layer, then etch resistance and mechanical strength are enhanced, but process complexity increases

Engineering Contradiction:
Improveetch resistanceVSAvoidprocess steps
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The nitridation process is applied selectively and locally to the dielectric layer over the STI region to form the protection hard mask. Rather than nitriding the entire dielectric layer uniformly, the process is targeted specifically where protection is needed, which enhances etch resistance at the critical STI region while minimizing unnecessary process complexity elsewhere.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The protection hard masks effectively prevent damage to the STI regions, maintaining device performance and reducing the risk of leakage current by enhancing the etch resistance and mechanical strength of the oxide material.

Implementation Method 1

formed by nitridating a dielectric layer using directional plasma or thermal nitridation processes

Methodology Applied
Scientific EffectNitridation: Nitriding

Data Source

PatentUS20260047136A1Semiconductor device and method of forming thereof
Publication Date: 2026.02.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260047136A1 patent drawing
  • US20260047136A1 patent drawing
  • US20260047136A1 patent drawing

AI summary

A method of forming a semiconductor device includes a number of operations. A dielectric layer is formed over a plurality of nanostructures arranged in a vertical manner and an isolation structure adjacent the nanostructures. The dielectric layer is nitridated. A vertical portion of the nitridated dielectric layer over a sidewall of the nanostructure is removed, wherein a first horizontal portion of the nitridated dielectric layer remains over the isolation structure, and a second horizontal portion of the nitridated dielectric layer remains over a topmost one of the nanostructures. A source/drain region is formed through the second horizontal portion of the nitridated dielectric layer and the nanostructures. A gate structure is formed and wraps around the nanostructures.