Nitride Bump Removal in Replacement Gate Structure
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Solution Overview
Problem
The existing replacement gate process for NFETs and PFETs faces challenges with non-uniformity in etch rate and gate height due to nitride bump formation and removal, leading to dishing in iso/wide STI regions and the need for large overetches to ensure complete nitride removal.
Innovation Solution
The introduction of an extra 1:1 oxide:nitride dry etch or an oxide recess followed by nitride fill and selective dry etches to control nitride cap opening and removal, ensuring a planar nitride surface and reducing oxide loss in the STI regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP buff is used to remove nitride bumps, then nitride bumps are removed, but large dishing occurs in iso/wide STI regions
Solution Approach 1:
The patent replaces the mechanical CMP buffing process with a chemical selective etching process. The selective etch chemistry targets nitride material specifically while leaving oxide STI regions unaffected, thereby removing nitride bumps without causing dishing in the STI regions. This substitution of mechanical action with selective chemical action resolves the contradiction between effective nitride removal and maintaining STI region planarity.
2Manufacturing precision
If large overetch is performed during nitride RIE to ensure complete nitride removal, then nitride is completely removed, but polysilicon gate etching occurs
Solution Approach 1:
The patent performs preliminary actions to protect the polysilicon gate before the main nitride removal step. Specifically, a mandrel is formed and a protective layer is deposited over the polysilicon gate area before the selective nitride etch. This preliminary protection allows aggressive etching conditions to be used for complete nitride removal while preventing polysilicon gate etching through the protective barrier.
Solution Approach 2:
The patent introduces an intermediary protective layer (such as a deposited film or mandrel structure) that mediates between the etch chemistry and the polysilicon gate. This intermediary layer is selectively removed after nitride removal, allowing complete nitride etching while preventing direct contact between the etch chemistry and the polysilicon gate, thus avoiding gate etching.
3Manufacturing precision
If nitride caps are etched away to define NFET and PFET regions, then region definition is achieved, but nitride bump formation occurs at mask overlap areas
Solution Approach 1:
The patent converts the harmful effect of nitride bump formation into a beneficial process feature. Instead of viewing the bumps as defects to be eliminated, the methodology uses the bumps as indicators of mask overlap areas and processes them selectively. The selective etching step targets these bump areas specifically, using their elevated geometry and exposed nitride surfaces to achieve precise region definition while removing the bumps in a controlled manner.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves etch rate uniformity, reduces oxide loss in STI regions, allows for a single-tool process, and enhances gate height control, preventing nitride liner divot formation and improving CMP process margins.
Implementation Method 1
performing a first dry etch including a 1:1 dry etch of the PMD and the nitride bump
Implementation Method 2
a first chemical mechanical polishing (CMP) is performed down to the nitride bumps 115, and a second CMP and buff are performed to remove the nitride bumps
Implementation Method 3
a first chemical mechanical polishing (CMP) is performed down to the nitride bumps 115, and a second CMP and buff are performed to remove the nitride bumps
Implementation Method 4
the remaining nitride of the nitride caps 103 is removed by reactive ion etching (RIE) or remote plasma nitride etch
Data Source
AI summary
Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.