Group III Nitride Semiconductor C-Plane Exposure via Anisotropic Etching

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Solution Overview

Problem

It is challenging to expose the c-plane of a group III nitride semiconductor substrate with minimal damage due to the difficulty in wet-etching its c-plane, which limits the design and manufacturing of semiconductor devices.

Innovation Solution

A method involving dry-etching to form a groove on the c-plane semiconductor substrate, followed by wet-etching the inner surface of the groove using an etchant with a lower etching rate for the c-plane, allowing the c-plane to be exposed while minimizing damage, as the etching primarily progresses on the side surfaces other than the c-plane.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wet-etching is performed to remove damaged layer from the c-plane, then the damaged layer can be removed, but the etching rate is too slow and the process becomes impractical

Engineering Contradiction:
Improvedamage removal effectivenessVSAvoidetching efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies local quality by making the etching rate direction-dependent. The etchant is designed to etch non-c-plane surfaces (side surfaces of the groove) at a high rate while etching the c-plane surface at a very low rate. This allows selective removal of damaged layers from side surfaces without significantly etching the c-plane, resolving the contradiction between effective damage removal and practical processing speed.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If the c-plane is exposed to remove damaged layer, then the device design flexibility is improved, but the c-plane is difficult to wet-etch so damage removal is ineffective

Engineering Contradiction:
Improvedevice design flexibilityVSAvoiddamage layer removal effectiveness
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent inverts the conventional approach by not directly etching the c-plane to remove damage. Instead, it forms a groove structure where the side surfaces (non-c-plane) are etched to remove damaged layers, while the c-plane remains relatively intact. This inverted approach allows the c-plane to be exposed for device design flexibility while avoiding the problem of ineffective c-plane etching.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively exposes the c-plane with reduced damage, enabling the formation of semiconductor devices with lower channel resistance and improved device characteristics by creating a channel in a less damaged region.

Implementation Method 1

wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region

Methodology Applied
Scientific EffectWet etching:

Implementation Method 2

the etchant having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane

Methodology Applied
Scientific EffectAnisotropic etching:

Implementation Method 3

forming a groove on the main surface by dry-etching the main surface

Methodology Applied
Scientific EffectDry etching:

Data Source

PatentUS11107691B2Method of manufacturing semiconductor device
Publication Date: 2021.08.31 DENSO CORP
  • US11107691B2 patent drawing
  • US11107691B2 patent drawing
  • US11107691B2 patent drawing

AI summary

A method of manufacturing a semiconductor device is provided, and the method may include: preparing a semiconductor substrate constituted of a group III nitride semiconductor, a main surface of the semiconductor substrate being a c-plane; forming a grove on the main surface by dry dry-etching the main surface; and wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region, the etching having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane of the semiconductor substrate.