Self-aligning Nitride Charge Storage in Polysilicon Memory Gates
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Solution Overview
Problem
Existing non-volatile semiconductor memory devices with charge storage layers are slow and inefficient in programming and erasing operations.
Innovation Solution
The introduction of a CMOS non-volatile memory cell design featuring a substrate with a select gate, multiple polysilicon gates, and a self-aligning nitride charge storage layer, where the additional polysilicon gates enhance channel hot electron injection and band-to-band tunneling hot hole injection, improving current density and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional charge storage structures are used in non-volatile memory devices, then the memory cells can be formed using standard CMOS processes, but the programming and erasing operations are slow and inefficient
Solution Approach 1:
The gate structure is segmented into multiple polysilicon gates (first polysilicon gate, second polysilicon gate, third polysilicon gate) that can be independently controlled. This segmentation allows simultaneous application of different voltages to different gate segments, enabling parallel charge injection and extraction operations that significantly improve programming and erasing speeds compared to conventional single-gate structures.
Solution Approach 2:
The invention transitions from a planar charge storage approach to a three-dimensional configuration where charge storage layers are positioned between multiple gates in the vertical dimension. This multi-layer gate structure enables charge injection and extraction from multiple directions simultaneously, increasing the effective operation area and improving programming/erasing efficiency without increasing chip area.
2Productivity
If additional polysilicon gates are added to enhance charge injection, then current density and operational efficiency improve, but device complexity increases
Solution Approach 1:
Multiple polysilicon gates are merged into a single integrated memory cell structure, sharing common charge storage layers and diffusion regions. This merging approach allows the gates to work协同 (cooperatively) to achieve enhanced charge injection and extraction while avoiding the need for separate control circuits for each gate, thus improving operational efficiency without proportionally increasing device complexity.
Solution Approach 2:
The additional polysilicon gates serve multiple functions: they enable independent control of charge injection and extraction, provide separate programming and erasing pathways, and allow for voltage distribution strategies that reduce overall power consumption. This multi-functionality justifies the increased structural complexity by delivering superior operational efficiency and flexibility.
3Reliability
If multiple polysilicon gates are used to improve charge storage control, then program/erase window is maintained under 2 Volts operation, but manufacturing precision requirements increase
Solution Approach 1:
The charge storage layers are pre-formed between the polysilicon gates before final gate patterning and alignment steps. This preliminary formation of the charge storage structure establishes the spatial relationships and dimensions early in the fabrication process, providing a reference framework that guides subsequent gate alignment steps and reduces the cumulative impact of manufacturing variations.
Solution Approach 2:
The structure utilizes self-aligned fabrication techniques where the positions of the polysilicon gates are automatically determined by the underlying charge storage layers and diffusion regions. This self-alignment mechanism eliminates the need for complex multi-step alignment procedures, maintaining manufacturing feasibility while achieving the precise gate positioning required for reliable low-voltage operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the program and erase performance of memory cells by increasing current density and maintaining an acceptable program/erase window under 2 Volts operation, improving memory cell efficiency compared to prior art.
Implementation Method 1
channel hot electrons from the source region 157-1 may enter the charge storage region 155-2 by traveling through the channel region 156
Implementation Method 2
inducing band-to-band tunneling holes to enter the charge storage structure 155-2
Data Source
AI summary
A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.