Nitride Semiconductor Current Aperture Without Etching

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Solution Overview

Problem

Existing semiconductor devices face challenges in forming current apertures without etching processes, which can lead to surface states and reduced yield rates.

Innovation Solution

A nitride-based semiconductor device is designed with a single III-V group semiconductor layer that includes a high resistivity region and a current aperture, where the high resistivity region is formed by introducing more metal oxides than the current aperture, allowing for the formation of a current blocking layer without etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If an etching process is used to form current apertures, then the device structure can be defined, but surface states are generated and yield rates are reduced

Engineering Contradiction:
Improvecurrent aperture definitionVSAvoidyield rate
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent replaces the mechanical etching process with a chemical oxidation process. The current blocking layer is formed by oxidizing the III-V semiconductor layer through exposure to oxygen plasma or oxygen-containing gas, which converts the semiconductor material into an insulating oxide layer without the need for physical etching. This substitution eliminates the generation of surface states associated with etching while still achieving precise definition of the current aperture regions.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent utilizes changes in the oxidation parameters (such as oxygen plasma power, treatment time, and temperature) to control the formation and thickness of the current blocking layer. By adjusting these parameters, the oxidation process can selectively form insulating regions with precise dimensions and electrical properties, achieving the required manufacturing precision without compromising device yield.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If a complex etching process is used to form current blocking layers, then current apertures can be defined, but the manufacturing process becomes more complex and yield rates decrease

Engineering Contradiction:
Improvecurrent blocking layer formationVSAvoidmanufacturing process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines the current blocking layer formation with the existing oxidation steps in the manufacturing process. The oxidation process that is already used for other purposes (such as surface preparation or interface formation) is extended to simultaneously create the current blocking regions. This merging of functions reduces the total number of process steps and simplifies the manufacturing workflow while maintaining the required precision.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The oxidation process is designed to serve multiple functions: it forms the current blocking layer, defines the current aperture boundaries, and prepares the surface for subsequent electrode deposition. This multi-functional approach eliminates the need for separate etching and blocking layer formation steps, thereby reducing process complexity and improving manufacturing efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If traditional methods are used to form current blocking layers, then current apertures can be created, but the profile control of the blocking layer is difficult

Engineering Contradiction:
Improvecurrent aperture creationVSAvoidcurrent blocking layer profile
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The patent applies local quality by creating spatial variations in the oxidation conditions across the semiconductor layer. By controlling the oxygen plasma distribution and exposure uniformity, the oxidation process forms current blocking regions with specific lateral and vertical profiles. The oxidation can be localized to certain areas while leaving other regions unaffected, enabling precise control over the shape and dimensions of the current apertures and blocking layers.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes the dynamic nature of the oxidation process to achieve profile control. The oxidation rate and extent can be dynamically adjusted during the process by controlling oxygen plasma parameters, treatment time, and temperature. This dynamic control allows the formation of current blocking layers with optimized profiles that match the desired device geometry, overcoming the limitations of static etching processes.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves the yield rate by eliminating the need for etching and allows for easy profiling of the current blocking layer, making it adaptable to various device designs.

Implementation Method 1

An oxidizing process is performed to laterally oxidize the single III-V group semiconductor layer

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS12289904B2Nitride-based semiconductor device and method for manufacturing the same
Publication Date: 2025.04.29 INNOSCIENCE (SUZHOU) TECH CO LTD
  • US12289904B2 patent drawing
  • US12289904B2 patent drawing
  • US12289904B2 patent drawing

AI summary

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a lattice layer, a third nitride-based semiconductor layer, a first source electrode and a second electrode, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The lattice layer is disposed between the first and second nitride-based semiconductor layers and doped to the first conductivity type. The lattice layer comprises a plurality of first III-V layers and second III-V layers alternatively stacked. Each of the first III-V layers has a high resistivity region and a current aperture enclosed by the high resistivity region. The high resistivity region comprises more metal oxides than the current aperture. At least two of the current apertures have different dimensions such that interfaces formed between the high resistivity regions and the current apertures misalign with each other. The gate electrode aligns with the current aperture.