Nitride Semiconductor Current Aperture Structure Without Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nitride-based semiconductor devices face challenges in efficiently forming current blocking layers without the need for etching processes, which can lead to surface states and reduced yield rates.
Innovation Solution
The introduction of a nitride-based semiconductor device structure that includes a single III-V group semiconductor layer with a high resistivity region and a current aperture, where the high resistivity region is formed by introducing oxygen atoms, allowing for the formation of a current blocking layer without etching, thereby improving yield and flexibility in device design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etching process is used to form a current blocking layer, then the current blocking function is achieved, but surface states are created and yield rates are reduced
Solution Approach 1:
The patent extracts the harmful etching process from the fabrication sequence and replaces it with an oxidation-based approach. The current blocking layer is formed through oxidation of the III-V semiconductor layer rather than removal via etching, thereby eliminating surface state creation while maintaining current blocking functionality.
Solution Approach 2:
The patent changes the fundamental parameter of layer formation from subtractive (etching) to additive/transformative (oxidation). By controlling oxidation conditions and timing, the current blocking layer is formed in-situ without creating surface states, thus improving yield rate while achieving the desired electrical isolation.
2Adaptability or versatility
If a fixed device structure is used, then manufacturing is simplified, but adaptability to different device designs is reduced
Solution Approach 1:
The patent introduces dynamic controllability in the oxidation process, allowing the current blocking layer profile to be adjusted based on different device design requirements. By controlling oxidation time, temperature, and atmosphere, the layer profile can be dynamically optimized for various device configurations without changing the fundamental fabrication approach.
Solution Approach 2:
The oxidation-based current blocking layer formation method serves multiple functions: it provides electrical isolation, defines device boundaries, and can be adjusted for different device geometries. This universal approach replaces multiple specialized processes with a single versatile oxidation step that adapts to various device design needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a current blocking layer that improves the yield rate and allows for easier profile adjustments to comply with different device designs, while avoiding the destructive etching process.
Implementation Method 1
The high resistivity region comprises more metal oxides than the current aperture so as to achieve a resistivity higher than that of the current aperture
Data Source
AI summary
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a lattice layer, a third nitride-based semiconductor layer, a first source electrode and a second electrode, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The lattice layer is disposed between the first and second nitride-based semiconductor layers and doped to the first conductivity type. The lattice layer comprises a plurality of first III-V layers and a plurality of second III-V layers alternatively stacked. Each of the first III-V layers has a high resistivity region and a current aperture enclosed by the high resistivity region. The high resistivity region comprises more metal oxides than the current aperture. Interfaces formed between the high resistivity regions and the current apertures among the first III-V layers align with each other. The gate electrode aligns with the current aperture.