Group III Nitride Epitaxial Layers on Silicon Substrates
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Solution Overview
Problem
The challenge lies in forming high-quality, thick gallium nitride epitaxial layers on large silicon substrates, which is hindered by stress levels, thermal expansion coefficient mismatches, and high defect densities, limiting the breakdown voltage of devices like FETs and HEMTs.
Innovation Solution
The approach involves forming non-continuous epitaxial layers with 'expansion joints' using mesas and trenches on the substrate, accompanied by nucleation layers and dielectric films, allowing for stress accommodation and integration with standard CMOS processing tools, enabling thicker nitride layers on larger substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gallium nitride epitaxial layers are formed over large silicon substrates using conventional techniques, then the substrate area is充分利用, but the layer quality deteriorates due to stress levels, thermal expansion coefficient mismatches, and high defect densities
Solution Approach 1:
The patent divides the continuous epitaxial layer into segmented regions separated by dielectric material layers. These dielectric layers act as expansion joints that segment the nitride layer, allowing each segment to independently accommodate thermal expansion and stress without affecting the entire wafer. This segmentation enables formation of high-quality thick nitride layers over large substrate areas by isolating stress and defect propagation.
2Reliability
If the gallium nitride layer thickness is increased to provide higher breakdown voltage, then the device performance improves, but the manufacturing difficulty increases due to stress and defect accumulation
Solution Approach 1:
The patent incorporates dielectric material layers between the silicon substrate and the gallium nitride epitaxial layer, and also between nitride layers themselves. These dielectric layers serve as cushioning elements that accommodate thermal expansion coefficient mismatches and reduce stress accumulation before they can propagate through the structure. This beforehand cushioning enables formation of thicker nitride layers with higher breakdown voltage while maintaining manufacturing feasibility.
3Reliability
If thick gallium nitride layers are formed to achieve high breakdown voltage, then the device reliability improves, but special processing tools are required which increases device complexity
Solution Approach 1:
The patent introduces dielectric material layers as intermediary elements between the silicon substrate and gallium nitride epitaxial layer. These intermediary layers mediate the thermal and mechanical stress interactions, allowing standard CMOS processing tools to form thick high-quality nitride layers without requiring specialized equipment. The dielectric intermediaries enable compatibility with conventional processing while achieving high breakdown voltage devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the formation of thicker gallium nitride layers, enhancing the breakdown voltage of semiconductor devices and facilitating their integration with conventional CMOS processing, overcoming the limitations of existing techniques.
Implementation Method 1
large thermal expansion coefficient mismatches
Implementation Method 2
high stress levels
Implementation Method 3
gallium nitride epitaxial layers are often formed over silicon-based substrates
Implementation Method 4
metal-organic chemical vapor deposition (MOCVD)
Data Source
AI summary
A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools.