Normally OFF Nitride FETs with Depopulated 2DEG Channels
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Solution Overview
Problem
Conventional silicon-based semiconductor field effect transistors (FETs) fail to meet the requirements for high power switching applications due to limitations in breakdown voltage, ON resistance, and tolerance to high junction temperatures and transients, while nitride-based FETs are difficult to configure as normally OFF switches with low defect concentrations at acceptable costs.
Innovation Solution
A normally OFF FET is designed using nitride semiconductor layers with a 2DEG current channel in a narrow band gap layer adjacent to a wide band gap layer, along with a potential modifying layer to depopulate electrons and a superlattice structure to moderate defects, allowing for low ON resistance and high breakdown voltage, and featuring a recessed gate configuration to control electron populations and reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon-based FETs are used for power switching applications, then manufacturing cost and ease of manufacture are improved, but breakdown voltage and tolerance to high junction temperatures deteriorate
Solution Approach 1:
The patent changes the material parameter from silicon to nitride semiconductor, fundamentally altering the band gap and breakdown characteristics to achieve high voltage capability while maintaining manufacturability through established nitride fabrication processes
Solution Approach 2:
The patent employs a composite heterostructure with multiple nitride layers (AlN, GaN, InGaN) with different band gaps and properties, where each layer contributes specific functions: AlN provides high breakdown voltage, GaN provides high electron mobility, and InGaN provides piezoelectric polarization for 2DEG formation
2Ease of manufacture
If silicon-based FETs are used for power switching applications, then ease of manufacture is improved, but operating temperature tolerance deteriorates
Solution Approach 1:
The patent changes the material's intrinsic temperature tolerance parameter by selecting nitride semiconductor with wide band gap, which inherently supports higher operating temperatures compared to silicon, enabling reliable operation at elevated junction temperatures
3Reliability
If nitride-based FETs are configured with 2DEG channels to reduce ON resistance, then ON resistance is improved, but leakage current increases
Solution Approach 1:
The patent applies local quality by creating 2DEG channels only in specific regions under the gate electrodes where low resistance is needed, while maintaining depleted regions in access areas to minimize leakage, achieving spatial optimization of conductive and insulating properties
Solution Approach 2:
The patent implements preliminary anti-action by using piezoelectric polarization in InGaN barriers to pre-deplete carrier concentrations in access regions before device operation, thereby preventing leakage current generation while preserving 2DEG channels for low-resistance conduction
4Reliability
If nitride-based FETs are configured as normally OFF switches, then safety and reliability are improved, but defect concentration increases
Solution Approach 1:
The patent changes the device's default state parameter from normally ON to normally OFF by engineering the band alignment and polarization fields in the heterostructure, creating a potential barrier that depletes the channel in the absence of gate voltage, achieving safe default operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FET achieves a normally OFF state with low ON resistance and high breakdown voltage, capable of supporting high currents and operating at elevated temperatures, while minimizing leakage currents and maintaining reliability during voltage and current transients.
Implementation Method 1
piezoelectric and spontaneous polarization of the layers are configured so that the FET is normally OFF
Implementation Method 2
piezoelectric and spontaneous polarization of the layers are configured so that the FET is normally OFF
Implementation Method 3
a polarization that generates an electrostatic field in the second nitride layer having a direction that causes electron drift towards the first heterojunction
Implementation Method 4
Voltage relative to a common ground voltage applied to the gate generates an electric field in the FET that controls the resistance of the channel
Data Source
Figure 1A
Figure 1B~1C
Figure 1D
AI summary
A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate.