Nitride Semiconductor FET Gate Insulator Heat Treatment
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Solution Overview
Problem
Field effect transistors using nitride semiconductors face challenges in achieving a sufficiently large drain current due to high-concentration interface trap levels at the interface between the gate insulating film and the AlGaN barrier layer, which reduces controllability of the drain current by gate voltage.
Innovation Solution
A channel layer and barrier layer with specific compositions are formed, and a gate insulating film with a larger band gap is applied, followed by heat treatment with a positive voltage applied to the gate electrode to reduce interface trap levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate insulating film is deposited on the upper surface of the AlGaN barrier layer using a simple deposition process, then the manufacturing process is simple and easy to implement, but a high-concentration interface trap level is formed at the interface between the gate insulating film and the AlGaN barrier layer, which reduces the controllability of drain current by gate voltage and prevents sufficient drain current from being obtained
Solution Approach 1:
The patent applies a preliminary action by performing heat treatment on the gate insulating film before final deposition or formation. This pre-treatment modifies the substrate surface properties, reducing interface trap levels that would otherwise form during subsequent deposition processes. The heat treatment prepares the surface in advance to prevent harmful interface trap formation rather than addressing it after the fact.
Solution Approach 2:
The patent changes physical parameters by applying heat treatment at specific temperatures (typically 400-600°C) to modify the interface properties between the gate insulating film and AlGaN barrier layer. This thermal parameter change reduces interface trap concentrations from high levels to acceptable levels, thereby improving drain current controllability while maintaining manufacturing feasibility.
2Device complexity
If heat treatment is performed without applying voltage to the gate electrode, then the manufacturing process is simpler, but interface trap levels are not sufficiently reduced and drain current remains insufficient
Solution Approach 1:
The patent merges two processes - heat treatment and voltage application - into a single combined treatment step called bias heat treatment or annealing. By applying a positive voltage to the gate electrode during heat treatment, the process simultaneously performs thermal activation and electrical field effect, synergistically reducing interface trap levels more effectively than either process alone would achieve.
Solution Approach 2:
The patent creates a composite treatment approach by combining thermal energy (heat treatment) and electrical energy (applied voltage) to produce a combined effect that reduces interface trap levels more effectively. This composite methodology leverages both thermal and electrical fields working together on the interface region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described configuration effectively reduces interface trap levels, enabling a sufficiently large drain current in nitride semiconductor field effect transistors.
Implementation Method 1
heat treatment is performed while a positive voltage is being applied to the gate electrode
Data Source
AI summary
Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Alx1Iny1Ga1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Alx2Iny2Ga1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.