Nitride FET Active-Region Layout for Lower Drain Leakage
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Solution Overview
Problem
Conventional nitride semiconductor FETs experience high drain leakage current due to incomplete carrier removal at the interface between active and inactive regions, leading to reduced performance and reliability in high-voltage, high-frequency applications.
Innovation Solution
The semiconductor device incorporates a substrate with first and second nitride semiconductor layers, each with a band gap greater than the other, and third active regions connected to the first and second active regions, featuring P-type impurities to reduce two-dimensional electron gas generation and leakage current, with the third nitride semiconductor layer extending over the active regions to connect the P-type layers and prevent carrier leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If multiple active regions with FETs are provided spaced apart from one another and connected in parallel, then heat generation is distributed and temperature increase is reduced, but device structure becomes more complex
Solution Approach 1:
The semiconductor device is divided into multiple active regions (first active region, second active region, third active region) that are spaced apart from each other. Each active region contains FETs connected in parallel, which segments the heat-generating areas and distributes thermal load, thereby reducing temperature increase while maintaining functional complexity through modular segmentation.
2Object-affected harmful factors
If inactive region is provided to define active regions and reduce parasitic capacitance, then parasitic capacitance is reduced, but carrier accumulation occurs at the interface between active and inactive regions causing high drain leakage current
Solution Approach 1:
A fourth active region is introduced as an intermediary between the first active region and the inactive region. This intermediate active region acts as a buffer zone that prevents direct interface formation between active and inactive regions, thereby eliminating the carrier accumulation problem and reducing drain leakage current while still maintaining the benefits of parasitic capacitance reduction through proper spatial arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces drain leakage current by eliminating the leakage path at the interface, enhancing the reliability and performance of the FETs in high-voltage, high-frequency operations.
Implementation Method 1
a high-concentration two-dimensional electron gas (2DEG) layer is generated at the junction interface due to spontaneous polarization and piezo polarization
Implementation Method 2
a high-concentration two-dimensional electron gas (2DEG) layer is generated at the junction interface due to spontaneous polarization and piezo polarization
Implementation Method 3
a high-concentration two-dimensional electron gas (2DEG) layer is generated at the junction interface due to spontaneous polarization and piezo polarization
Implementation Method 4
the portion of the first P-type nitride semiconductor layer and the portion of the second P-type nitride semiconductor layer are connected to each other via the portions of the third nitride semiconductor layer, in the first active region, the second active region, and the third active regions
Data Source
AI summary
A semiconductor device includes third active regions that connect two finger-end portions of field effect transistors (FETs) spaced apart from each other, and includes, above the third active regions, portions of a third nitride semiconductor layer that includes P-type impurities.