Nitride Transistor Gate Control to Prevent Simultaneous On-States
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Solution Overview
Problem
Transistors made of nitride semiconductor materials often have a depletion type structure, which complicates the design of power control semiconductor devices, necessitating a circuit configuration that combines depletion and enhancement type transistors in series, but existing solutions fail to effectively prevent simultaneous on-states and are susceptible to external noise.
Innovation Solution
A semiconductor device comprising a depletion type transistor and an enhancement type transistor connected in series, with a gate control circuit controlling the second transistor's gate voltage to prevent simultaneous on-states and integrating them within a sealed package to reduce parasitic inductance and noise susceptibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a power control semiconductor device uses a circuit configuration combining depletion and enhancement type transistors in series, then the device can achieve proper power control functionality, but the device becomes susceptible to external noise and may experience simultaneous on-states
Solution Approach 1:
The patent integrates the depletion type transistor, enhancement type transistor, and gate control circuit into a single sealed package, merging multiple components that were previously separate. This integration reduces the physical distance between components, minimizing parasitic inductance and making the device less susceptible to external noise while preventing simultaneous on-states through coordinated control
Solution Approach 2:
The gate control circuit acts as an intermediary between the depletion type transistor and enhancement type transistor, coordinating their switching operations to prevent simultaneous on-states. The circuit controls the gate voltage of the enhancement type transistor based on the state of the depletion type transistor, ensuring proper sequencing
2Reliability
If a power control semiconductor device uses a circuit configuration combining depletion and enhancement type transistors in series, then the device can achieve proper power control functionality, but the device complexity increases
Solution Approach 1:
The patent combines multiple transistors and control circuits into a single integrated semiconductor device structure. By integrating the depletion type transistor, enhancement type transistor, and gate control circuit onto the same substrate and sealing them together, the patent reduces the overall system complexity despite the sophisticated internal configuration
Solution Approach 2:
The gate control circuit automatically coordinates the switching of the enhancement type transistor based on the state of the depletion type transistor without requiring external control. This self-service mechanism simplifies the overall system by eliminating the need for external control logic
3Object-affected harmful factors
If the transistor and control circuit are integrated within a sealed package, then parasitic inductance and noise susceptibility are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent integrates multiple components (depletion type transistor, enhancement type transistor, gate control circuit) into a single sealed package structure. This merging approach reduces parasitic inductance by minimizing trace lengths and interconnections, while the standardized packaging process manages the manufacturing complexity
Data Source
AI summary
A semiconductor device includes a substrate, a first transistor of a depletion type, a second transistor of an enhancement type, and a gate control circuit. The first and second transistors are provided on the substrate and each include a channel region of a first conductivity type. The first and second transistors are connected in series. The channel region of the first transistor includes a nitride semiconductor. The second transistor operates via an inversion layer of a second conductivity type induced in the channel region thereof. The gate control circuit is connected to a gate electrode of the second transistor. The substrate includes a gate terminal and a power supply terminal. The gate terminal is electrically connected to a gate electrode of the first transistor. The power supply terminal is electrically connected to a connection part between the first transistor and the second transistor.