Nitride Semiconductor Gate Electrode Leakage Reduction
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Solution Overview
Problem
Conventional nitride semiconductor devices with p-type GaN gate electrodes suffer from increased leakage current and limited gate voltage sweep range due to the low built-in voltage of the PN junction, limiting their normally-off characteristics and power conversion efficiency.
Innovation Solution
A nitride semiconductor device with p/n-type nitride layer gate electrodes is developed, featuring a heterojunction structure with a 2DEG channel, p-type, and n-type nitride layers, where the gate electrode is in contact with the n-type layer, forming an npn junction to suppress gate leakage current and enhance turn-on performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type GaN gate electrode is used on an AlGaN/GaN HEMT structure, then normally-off characteristics are achieved by depleting 2DEG below the gate, but gate leakage current increases during turn-on operation
Solution Approach 1:
The gate electrode is segmented into a p-type GaN layer and an n-type GaN layer stacked vertically. The p-type layer provides the depletion region for normally-off characteristics, while the n-type layer serves as a low-resistance contact layer that reduces gate leakage current during turn-on operation.
Solution Approach 2:
The gate electrode uses a composite structure combining p-type and n-type GaN layers. This composite material approach allows the gate to simultaneously exhibit high-resistance depletion characteristics (from p-type) and low-resistance contact properties (from n-type), resolving the contradiction between normally-off operation and leakage current reduction.
2Reliability
If a p-type GaN gate electrode is used, then normally-off structure is achieved, but gate voltage sweep range is limited to lower than built-in voltage of PN junction
Solution Approach 1:
The gate electrode is divided into p-type and n-type layers, where the n-type layer extends the voltage sweep range by providing a low-resistance path that allows higher gate voltages to be applied without being limited by the built-in voltage of a single PN junction.
Solution Approach 2:
The invention changes the electrical parameters of the gate electrode by introducing an n-type layer with different doping characteristics. This parameter change allows the gate to operate over a wider voltage range while maintaining the normally-off characteristics provided by the p-type layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves normally-off characteristics with reduced gate leakage current and increased gate sweep voltage, improving turn-on current and power conversion efficiency, while simplifying manufacturing processes by using the same metal material for all electrodes.
Implementation Method 1
a nitride semiconductor layer formed by a heterojunction of a first nitride layer and a second nitride layer, which includes a material with a wider energy band gap than a material of the first nitride layer, and having a two-dimensional electron gas (2DEG) channel formed near a junction interface
Implementation Method 2
a technique of making a normally-off structure by employing a gate electrode structure using p-type GaN on an AlGaN/GaN HEMT structure... a GaN HFET implements normally-off by forming p-type GaN or p-type AlGaN in a gate electrode to deplete 2DEG below the gate
Implementation Method 3
using p/n-type nitride semiconductors as gate electrodes... forming an npn junction to suppress gate leakage current
Data Source
AI summary
The present invention relates to a nitride semiconductor device One aspect of the present invention provides a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a p-type nitride layer formed on the nitride semiconductor layer between the source and drain electrodes; an n-type nitride layer formed on the p-type nitride layer; and a gate electrode formed between the source and drain electrodes to be close to the source electrode and in contact with the n-type nitride layer so that a source-side sidewall thereof is aligned with source-side sidewalls of the p-type and n-type nitride layers.