Nitride HEMT Field Plate Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-electron-mobility transistors (HEMTs) face challenges in miniaturization while maintaining reliability due to parasitic capacitance issues, which affect the electrical properties of nitride-based semiconductor devices used in high power and high frequency applications.
Innovation Solution
The semiconductor device incorporates a nitride-based transistor with three metal layers and electrode pads, featuring a configuration with two field plates to improve electric field distribution, reducing parasitic capacitance by vertically overlapping the first field plate with the gate electrode and laterally spacing the second field plate, thereby enhancing electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the device is miniaturized to meet design requirements, then the device size is reduced, but parasitic capacitance increases and reliability deteriorates
Solution Approach 1:
The patent introduces a third metal layer positioned above the second metal layer, creating a vertical stacking configuration. This three-dimensional arrangement allows the source and drain electrodes to be separated in the vertical dimension rather than only in the horizontal plane, effectively reducing parasitic capacitance while maintaining a compact footprint. The field plates in the third layer are positioned to overlap with the gate electrode vertically, achieving electric field control without increasing the lateral device area.
Solution Approach 2:
The third metal layer is divided into first and second patterns that are spaced apart from each other, with the first pattern forming the source field plate and the second pattern forming the drain field plate. This segmentation allows independent optimization of source and drain regions, enabling better electric field distribution and reduced parasitic capacitance between source and drain while maintaining compact device dimensions.
2Reliability
If field plates are positioned to improve electric field distribution, then electrical properties are enhanced, but parasitic capacitance may increase
Solution Approach 1:
The field plates in the third metal layer are positioned with specific local characteristics: the first field plate pattern is vertically aligned with the gate electrode to provide localized electric field control at the source region, while the second field plate pattern is laterally spaced from the gate electrode to control the drain region. This localized positioning optimizes electric field distribution in specific areas while minimizing overall parasitic capacitance.
Solution Approach 2:
The configuration creates asymmetric positioning of field plates relative to the gate electrode: the source field plate has vertical overlap with the gate, while the drain field plate is laterally offset. This asymmetric arrangement allows different electric field control strategies for source and drain regions, improving electrical properties while managing parasitic capacitance through differentiated positioning.
Data Source
AI summary
A semiconductor device includes a nitride-based transistor, a first metal layer, a second metal layer, a third metal layer, a source pad, and a drain pad. The first metal layer is disposed over the nitride-based transistor. The second metal layer is disposed over the first metal layer. The third metal layer is disposed over the second metal layer and includes a first pattern and a second pattern which are spaced apart from each other. The source pad is immediately above the first metal layer, the second metal layer, and the first pattern of the third metal layer and is electrically coupled with the nitride-based transistor. The drain pad is immediately above the first metal layer, the second metal layer, and the second pattern of the third metal layer and is electrically coupled with the nitride-based transistor.