Nitride HEMT Heterojunction Layout for Lower On-State Resistance

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Solution Overview

Problem

Current nitride-based semiconductor devices with HEMT structures face challenges in reducing on-state resistance and ensuring reliable carrier injection due to limited channel configurations, which affects their performance in high-power and high-frequency applications.

Innovation Solution

A nitride-based semiconductor device with a vertical HEMT structure featuring a first nitride-based semiconductor layer with doped barrier regions defining an aperture, a nitride-based multiple semiconductor layer structure with separated heterojunctions, and a gate electrode aligned with the aperture, allowing for four-channel configurations that enhance carrier injection and reduce on-state resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional HEMT structure with limited channel configuration is used, then the device structure is simple, but the on-state resistance is high and carrier injection reliability is poor

Engineering Contradiction:
Improvecarrier injection reliabilityVSAvoidheterojunction configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the channel into multiple independent heterojunction segments (first heterojunction and second heterojunction) that are separated from each other. Each heterojunction acts as an independent carrier injection channel, allowing carriers to be injected through multiple paths simultaneously. This segmentation improves carrier injection reliability because if one channel fails, others can still function, while the increased structural complexity is justified by the performance gains.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a single-channel configuration is used, then the device structure is simple, but the on-state resistance is high

Engineering Contradiction:
Improveon-state resistanceVSAvoidchannel configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a multi-channel configuration by creating separate first and second heterojunctions that function as independent parallel channels. This allows multiple carrier streams to flow simultaneously through different channels, effectively reducing the total on-state resistance. The segmentation principle transforms a single high-resistance path into multiple lower-resistance parallel paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple heterojunction channels into a single integrated device structure where the first and second heterojunctions work together. The merging of multiple carrier injection channels into one unified device achieves lower overall resistance while maintaining the benefits of multi-channel operation, balancing complexity reduction with performance improvement.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If heterojunctions are placed close together or overlapping, then the device area is reduced, but carrier injection efficiency decreases

Engineering Contradiction:
Improvecarrier injection efficiencyVSAvoiddevice area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent segments the heterojunctions into separated first and second heterojunctions with distinct spatial locations. This separation ensures that each heterojunction has sufficient space for effective carrier injection without interference from adjacent heterojunctions, maintaining high carrier injection efficiency. The segmented arrangement prioritizes functional performance over compactness.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The four-channel configuration reduces on-state resistance and ensures reliable carrier injection even if one channel fails, improving the device's performance in high-power and high-frequency applications by forming an electron accumulation layer for efficient carrier transport.

Implementation Method 1

III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region

Methodology Applied
Scientific EffectHeterojunction:

Implementation Method 2

heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region

Methodology Applied
Scientific EffectQuantum well:

Implementation Method 3

quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region

Methodology Applied
Scientific EffectTwo-dimensional electron gas (2DEG):

Implementation Method 4

at least two doped barrier regions defining an aperture in the drift region

Methodology Applied
Scientific EffectDoping: Dopants

Implementation Method 5

forming an electron accumulation layer for efficient carrier transport

Methodology Applied
Scientific EffectElectron accumulation layer:

Data Source

PatentUS20240055509A1Nitride-based semiconductor device and method for manufacturing the same
Publication Date: 2024.02.15 INNOSCIENCE (SUZHOU) TECH CO LTD
  • US20240055509A1 patent drawing
  • US20240055509A1 patent drawing
  • US20240055509A1 patent drawing

AI summary

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a nitride-based multiple semiconductor layer, a gate electrode, a gate insulator layer, and a source electrode. The first nitride-based semiconductor layer includes a drift region and at least two doped barrier regions defining an aperture in the drift region. The nitride-based multiple semiconductor layer structure is disposed over the first nitride-based semiconductor layer and has a first heterojunction and a second heterojunction which are separated from each other. The gate electrode is received by the nitride-based multiple semiconductor layer structure and vertically aligns with the aperture in the drift region. The gate insulator layer is disposed between the nitride-based multiple semiconductor layer structure and the gate electrode. The source electrode is disposed over the first nitride-based semiconductor layer and abuts against the first and second heterojunctions of the nitride-based multiple semiconductor layer structure.