Nitride HEMT Shield Layer Structure for Dynamic On-Resistance Suppression
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Solution Overview
Problem
High electron mobility transistors (HEMTs) face a dynamic on-resistance peak issue, which affects their performance and yield rate, particularly in high power and frequency applications, due to parasitic p-n junction diodes and defects in the buffer layer.
Innovation Solution
A nitride-based semiconductor device configuration is introduced, featuring a substrate with a buffer layer, a shield layer with a higher bandgap isolation compound, and source/drain electrodes that extend downward to contact the buffer layer, reducing the impact of parasitic p-n junctions and defects, and improving the 2DEG region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional buffer layer structure is used in HEMT devices, then the manufacturing process is simpler, but parasitic p-n junction diodes and defects in the buffer layer cause dynamic on-resistance peak issues, reducing device performance and yield rate
Solution Approach 1:
The buffer layer is segmented into multiple distinct layers including a first buffer layer, a second buffer layer with a first nitride-based semiconductor layer, and a third buffer layer with a second nitride-based semiconductor layer. This segmentation allows each layer to be optimized for specific functions, reducing parasitic effects and defects while maintaining manufacturing feasibility through systematic layer-by-layer construction
Solution Approach 2:
Different regions of the buffer structure are assigned different doping types and material compositions tailored to local requirements. The first buffer layer uses p-type doping to suppress parasitic diodes, while subsequent layers use n-type doping to improve electron mobility. This local quality optimization reduces dynamic on-resistance peaks without requiring complete structural redesign
2Reliability
If the source/drain electrode extends downward to contact the buffer layer, then the impact of parasitic p-n junctions is reduced, but the manufacturing process requires additional steps to form the extended electrode structure
Solution Approach 1:
The source/drain electrode is formed to extend downward into the buffer layer before final electrode deposition. This preliminary extension creates pre-formed contact regions that facilitate subsequent electrode material deposition and reduce parasitic junction effects, making the overall manufacturing process more efficient despite the additional initial step
Solution Approach 2:
The source/drain electrode structure is nested within the buffer layer architecture, with the electrode extending downward to contact specific buffer regions. This nesting approach integrates the electrode formation with the buffer layer structure, allowing parasitic junction suppression to be achieved through the electrode's geometric configuration rather than separate structural modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the dynamic on-resistance peak, enhances the reliability and performance of HEMT devices, and simplifies the manufacturing process, leading to a higher yield rate and improved compatibility for mass production.
Implementation Method 1
a shield layer with a higher bandgap isolation compound
Implementation Method 2
effectively suppresses the dynamic on-resistance peak, enhances the reliability and performance of HEMT devices
Implementation Method 3
improving the 2DEG region
Data Source
AI summary
A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. A first nitride-based semiconductor layer is disposed over the buffer. A shield layer is disposed between the buffer and the first nitride-based semiconductor layer and includes a first isolation compound that has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, in which the first isolation compound is made of at least one two-dimensional material which includes at least one metal element. A second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The pair of S/D electrodes and the gate electrode are disposed over the second nitride-based semiconductor layer.