Nitride Heterojunction Circuit Biasing for Lower Dynamic Resistance

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Solution Overview

Problem

Current nitride-based semiconductor devices face challenges in yield rate and dynamic resistance issues, particularly in high-electron-mobility transistors (HEMTs), which hinder their suitability for mass production and efficient operation.

Innovation Solution

A nitride-based semiconductor circuit design is introduced, featuring a heterojunction between nitride-based semiconductor layers with a potential difference applied between the power supply line and the connection line, which reduces dynamic resistance and improves yield by forming a heterojunction and utilizing p-type dopants to manage parasitic diodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a conventional nitride-based semiconductor device structure is used, then the device can be manufactured with standard processes, but the yield rate is low and dynamic resistance issues occur

Engineering Contradiction:
Improveyield rateVSAvoiddynamic resistance stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies a potential difference between the substrate and connector by changing the electrical parameter configuration. This potential difference modifies the electrical characteristics of the device, reducing dynamic resistance and eliminating the dynamic resistance-on peak phenomenon, thereby improving both yield rate and operational reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an intermediary mechanism through the potential difference application that mediates between the substrate and connector. This intermediary electrical configuration helps manage parasitic diodes and stabilizes the device operation, resolving the contradiction between manufacturing yield and operational reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the device structure is modified to improve yield rate, then manufacturing efficiency increases, but device complexity increases

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidcircuit structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Rather than modifying the physical structure, the patent changes the electrical parameter configuration by applying a potential difference. This approach improves manufacturing yield without increasing device complexity, as the solution lies in the electrical biasing scheme rather than structural modification

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed design enhances the yield of nitride-based semiconductor circuits by reducing dynamic resistance and addressing issues caused by parasitic diodes, leading to improved performance and manufacturability.

Implementation Method 1

The HEMT utilizes a heterojunction interface between two materials having different bandgaps, and electrons are accumulated at the interface and form a two-dimensional electron gas (2DEG) region

Methodology Applied
Scientific EffectHeterojunction:

Implementation Method 2

utilizes a heterojunction interface between two materials having different bandgaps

Methodology Applied
Scientific EffectBandgap difference:

Implementation Method 3

The third nitride-based semiconductor layer is doped with p-type dopant. The first and third nitride-based semiconductor layers form one or more parasitic diodes

Methodology Applied
Scientific EffectP-type doping: Dopants

Data Source

PatentUS20240021715A1Semiconductor device and method for manufacturing the same
Publication Date: 2024.01.18 INNOSCIENCE (SUZHOU) TECH CO LTD
  • US20240021715A1 patent drawing
  • US20240021715A1 patent drawing
  • US20240021715A1 patent drawing

AI summary

A nitride-based semiconductor circuit includes a nitride-based semiconductor carrier, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, connectors, a connection line, and a power supply line. The first nitride-based semiconductor layer is disposed over the nitride-based semiconductor carrier. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The connectors are disposed on the second nitride-based semiconductor layer. The connection line electrically connects to one of the connectors. The power supply line electrically to the nitride-based semiconductor carrier. A heterojunction is formed between the first and the second nitride-based semiconductor layers. A potential difference is applied between the power supply line and the connection line.