Nitride Interdeck Pillars for Multideck 3D Stack Alignment
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Solution Overview
Problem
The aspect ratio limitations in vertical semiconductor structures hinder the density and number of layers in multideck stacks due to punch damage and misalignment issues in interdeck connections, which are exacerbated by processing methods used for electrical isolation.
Innovation Solution
Implementing a nitride interdeck layer with self-aligned pillars featuring sloped sidewalls and gradient doping to facilitate precise alignment and minimize punch damage, utilizing selective etching techniques to form funnel-shaped openings for improved electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processing is performed to control the properties of the interdeck layer for electrical isolation, then electrical isolation between decks is improved, but punch damage and misalignment of interdeck connections occur
Solution Approach 1:
The patent applies preliminary action by forming a recess in the interdeck layer before creating the through-opening. This pre-formed recess serves as a guide structure that ensures the punching tool aligns correctly with the underlying deck features, preventing misalignment while still providing electrical isolation. The recess is formed using selective etching that targets specific material properties without affecting the overall structural integrity.
Solution Approach 2:
The patent introduces an intermediary structure (the recess with exposed underlying layer) between the interdeck layer and the punching process. This intermediary feature acts as a reference plane that mediates the alignment between the isolation function and the connection function, allowing both electrical isolation and precise alignment to coexist.
2Productivity
If vertical structures are made taller to increase density, then layer capacity is improved, but aspect ratio limitations cause pillar tilt and reduced manufacturing precision
Solution Approach 1:
The patent solves the aspect ratio problem by introducing a horizontal dimension through the recess structure. Instead of relying solely on vertical pillar integrity, the recess creates a stepped configuration that allows taller vertical structures to be built while maintaining alignment through the horizontal reference plane provided by the recess bottom.
Solution Approach 2:
The patent segments the vertical structure into distinct sections: the interdeck layer with its recess, the through-opening, and the underlying deck features. This segmentation allows each component to be optimized independently - the recess provides alignment reference while the through-opening maintains electrical connection, enabling taller structures without compromising precision.
3Quantity of substance
If pitch between pillars is reduced to increase density, then space utilization is improved, but sidewall verticality becomes harder to maintain
Solution Approach 1:
The patent applies local quality by creating a recess only in specific locations where interdeck connections are needed, rather than modifying the entire interdeck layer uniformly. This localized modification provides alignment references precisely where required, allowing tighter pillar spacing elsewhere without compromising the verticality and alignment of the connection structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the line of sight for punch capabilities, reduces damage, and increases the critical dimension of interdeck connections, thereby improving the density and reliability of multideck semiconductor structures.
Implementation Method 1
a nitride layer between the first deck and the second deck, the nitride layer having a self-aligned pillar through the nitride layer to electrically connect the first deck to the second deck
Implementation Method 2
The nitride layer can have a gradient doping, with higher doping toward an outside of the nitride layer and lower doping toward a middle of the nitride layer
Implementation Method 3
utilizing selective etching techniques to form funnel-shaped openings for improved electrical connections
Data Source
AI summary
A semiconductor circuit includes multiple decks of semiconductor devices, each deck having multiple three-dimensional (3D) stacks. The semiconductor circuit has a nitride layer between the first deck and the second deck. The nitride layer has a self-aligned pillar through the nitride layer to electrically connect the first deck to the second deck. The nitride layer can have multiple sublayers, with a mirrored gradient doping, with lower doping toward the middle of the nitride layer and higher doping toward the outsides of the nitride layer that interfaces with the decks.