Nitride Layer Orientation for Self-Aligned Contact Process Margin
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Solution Overview
Problem
The increasing degree of integration in semiconductor devices reduces the process margin, making it difficult to form contact plugs using self-aligned contact processes, particularly due to high aspect ratios and the risk of SAC fail, where the gate structure or bit line is etched during contact hole formation.
Innovation Solution
A nitride layer is formed perpendicularly to the conductive patterns on a semiconductor substrate using wet etching, reducing the aspect ratio of self-aligned contacts and preventing SAC fail, while a contact spacer functions as an etch barrier during the formation of landing plug contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick nitride layer is deposited on the gate structure or bit line to prevent SAC fail, then the reliability of the contact hole formation is improved, but the aspect ratio of the semiconductor structure increases which decreases the process margin
Solution Approach 1:
The patent applies local quality by forming the nitride layer selectively only in the contact hole region where it is needed for etch protection, rather than depositing it uniformly across the entire gate structure. This localized formation prevents SAC fail while avoiding the increased aspect ratio that would result from a thick universal nitride layer.
Solution Approach 2:
The patent introduces a vertical nitride layer formed perpendicular to the conductive pattern, adding a new dimensional approach to etch protection. This vertical layer provides the necessary protection during contact hole etching without requiring a thick horizontal layer that would increase the aspect ratio of the semiconductor structure.
2Reliability
If a thick nitride layer is used as a hard mask to prevent gate or bit line etching, then the reliability of the self-aligned contact process is improved, but the aspect ratio of the contact hole increases making the etching process more difficult
Solution Approach 1:
The nitride layer is formed locally only where needed for protection during contact hole etching, providing gate structure protection without creating a uniformly thick layer that would complicate the contact hole formation process.
Solution Approach 2:
The vertical nitride layer is formed in advance before the contact hole etching process, establishing the necessary protective structure beforehand. This preliminary action ensures gate protection is in place while maintaining ease of contact hole formation.
3Productivity
If the degree of integration is increased to improve device density, then the productivity and device performance are improved, but the process margin decreases making the self-aligned contact process more difficult
Solution Approach 1:
By applying the nitride layer locally only in the contact hole region rather than universally, the patent enables higher integration density while preserving sufficient process margin for the self-aligned contact process.
Solution Approach 2:
The vertical orientation of the nitride layer provides an innovative dimensional approach that allows increased integration density while maintaining the necessary process margin for reliable contact hole formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures a wider process margin by reducing the aspect ratio of contact holes and preventing damage to the gate structure, enabling more reliable and efficient formation of contact plugs through wet etching instead of dry etching.
Implementation Method 1
a nitride layer is formed on the semiconductor substrate perpendicularly to a conductive pattern to form a contact plug by wet etching
Implementation Method 2
a contact spacer that is formed of a nitride layer material on side walls of the conductive pattern and the nitride layer. Thus, the contact spacer functions as an etch barrier during the forming of a landing plug contact hole
Data Source
AI summary
Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.