Nitride Semiconductor Layer Structure for Defect-Suppressed Vertical FETs

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Solution Overview

Problem

Conventional nitride semiconductor field effect transistors (FETs) suffer from crystal defects and yield deterioration due to pits on the regrown layer surface, leading to suboptimal electrical properties.

Innovation Solution

A nitride semiconductor device is designed with a substrate, first and second nitride semiconductor layers, an electron transport layer, an electron supply layer, and a gate electrode, where the second nitride semiconductor layer includes a current conducting portion and a current blocking portion with controlled impurity concentrations to suppress crystal defects and enhance pinch-off characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If regrowth of nitride semiconductor layers is performed to form vertical field effect transistors, then device structure is formed, but crystal defects occur and electrical properties deteriorate

Engineering Contradiction:
Improvedevice structure formationVSAvoidelectrical properties
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The nitride semiconductor layer is divided into multiple distinct portions: a current conducting portion with first conductivity type and a current blocking portion with second conductivity type. This segmentation allows different regions to perform different functions - the current conducting portion enables electron transport while the current blocking portion prevents defect propagation and current collapse, thereby resolving the contradiction between manufacturability through regrowth and electrical reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the nitride semiconductor layer are assigned different impurity concentrations and conductivity types. The current conducting portion has higher impurity concentration for better electron transport, while the current blocking portion has lower impurity concentration to block defects. This local differentiation improves electrical properties without compromising the overall device structure formation

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If regrowth is performed to form the transistor structure, then the device can be manufactured, but on resistance increases

Engineering Contradiction:
Improvetransistor structure formationVSAvoidon resistance
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The electron transport layer is designed with specific local properties: higher impurity concentration in the current conducting portion to enhance electron transport and reduce on resistance, while lower impurity concentration in the current blocking portion to prevent defect-related current collapse. This local quality differentiation resolves the contradiction between manufacturability and on resistance control

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If regrowth is used to create the vertical FET structure, then device fabrication is enabled, but pinch-off characteristics deteriorate

Engineering Contradiction:
Improvevertical FET structureVSAvoidpinch-off characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The nitride semiconductor layer is segmented into current conducting and current blocking portions with different conductivity types. The current blocking portion with opposite conductivity type creates effective potential barriers that improve pinch-off characteristics by preventing carrier leakage, while the current conducting portion maintains good electron transport. This segmentation resolves the contradiction between easy fabrication through regrowth and degraded pinch-off characteristics

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution improves electrical properties by reducing crystal defects, suppressing Schottky contact, and enhancing pinch-off characteristics, resulting in improved yield and reliability of the nitride semiconductor device.

Implementation Method 1

A channel is formed by a 2-dimensional electron gas (2DEG) generated in the regrown layer

Methodology Applied
Scientific Effect2-dimensional electron gas (2DEG):

Implementation Method 2

Nitride semiconductors such as gallium nitride (GaN) are widegap semiconductors with a large band gap, have a high dielectric breakdown electric field strength

Methodology Applied
Scientific EffectPolarization effect:

Implementation Method 3

crystal defects are suppressed by ion implantation to maintain a flat upper surface

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20230387288A1Nitride semiconductor device
Publication Date: 2023.11.30 PANASONIC HOLDINGS CORP
  • US20230387288A1 patent drawing
  • US20230387288A1 patent drawing
  • US20230387288A1 patent drawing

AI summary

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type which is provided above the substrate; a second nitride semiconductor layer which is provided above the first nitride semiconductor layer; an electron transport layer and an electron supply layer which are sequentially provided above the second nitride semiconductor layer; a third nitride semiconductor layer and a gate electrode which are sequentially provided above the electron supply layer; a source electrode; and a drain electrode, the second nitride semiconductor layer includes: a current conducting portion of the first conductivity type which is located below the third nitride semiconductor layer and includes a first impurity; and a current blocking portion which is provided about the current conducting portion, and the concentration of the first impurity in the electron transport layer is lower than the concentration of the first impurity in the current conducting portion.