Monolithic Group III-Nitride LED Overgrowth Without SAG Masks

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Solution Overview

Problem

Existing selective area growth (SAG) methods for forming Group III-nitride LEDs are highly dependent on substrate geometry, leading to variations in doping profiles and layer compositions, and may incorporate unwanted dopants from masking layers.

Innovation Solution

A mask-less overgrowth method is developed, where a first semiconducting layer with a mesa structure is formed, and a monolithic LED structure is grown over the growth surface to cover both the mesa and bulk semiconducting surfaces, reducing the need for precise calibration and minimizing contamination from mask layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If selective area growth (SAG) method is used to form Group III-nitride LEDs, then material can be grown selectively on exposed buffer layer portions, but local variations in doping profiles and layer compositions occur due to aperture size differences

Engineering Contradiction:
Improveselective growth capabilityVSAvoiddoping profile uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent removes the mask layer from the SAG process entirely. Instead of using a mask to define growth areas, the method grows semiconductor material directly on the buffer layer in desired patterns, eliminating the source of dopant contamination and geometry-dependent variations while maintaining selective growth capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the conventional SAG approach by removing the masking step and directly growing material in the desired patterns. This reversal eliminates the harmful effects of mask geometry on doping profiles while preserving the ability to form selective structures

Inventive Principle:
Principle #13The other way round (Inversion)

2Ease of manufacture

If selective area growth (SAG) method is used with patterned masks, then selective material growth is achieved, but unwanted dopants from mask layers are incorporated into the grown structure

Engineering Contradiction:
Improveselective growth capabilityVSAvoiddopant contamination
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes the mask layer from the fabrication process. By eliminating the mask, the source of unwanted dopant contamination (Si or O from SiNx or SiO2 masks) is removed, while selective growth is achieved through direct patterning of the grown structure

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent converts the harmful effect of mask-related dopant contamination into a benefit by removing the mask entirely. This eliminates the contamination source while the direct growth method provides cleaner material with controlled doping profiles

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Manufacturing precision

If SAG process is calibrated for one device geometry, then optimal doping profiles are achieved, but recalibration is required for different geometries

Engineering Contradiction:
Improvedoping profile controlVSAvoidgeometry flexibility
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal fabrication method that works across different device geometries without requiring recalibration. The direct growth approach on buffer layers produces consistent doping profiles regardless of the specific aperture size or device layout, making the process geometry-independent

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces local variations in doping and layer composition, enhances light extraction efficiency due to inclined facets, and eliminates the risk of dopant contamination from mask layers, resulting in improved LED precursors with increased reliability and efficiency.

Implementation Method 1

forming a monolithic LED structure on the growth surface of the first semiconducting layer such that the monolithic LED structure covers the mesa surface and the bulk semiconducting surface

Methodology Applied
Scientific EffectSelective area growth: Epitaxy

Data Source

PatentUS12278257B2Light Emitting Diode and method of forming a Light Emitting Diode
Publication Date: 2025.04.15 PLESSEY SEMICON LTD
  • US12278257B2 patent drawing
  • US12278257B2 patent drawing
  • US12278257B2 patent drawing

AI summary

A method of forming a Light Emitting Diode (LED) precursor comprising: forming a first semiconducting layer comprising a Group III-nitride on a substrate, selectively removing a portion of the first semiconducting layer to form a mesa structure, and forming a monolithic LED structure. According to the method, the first semiconducting layer has a growth surface on an opposite side of the first semiconducting layer to the substrate. According to the method, the first semiconducting layer is selectively removed to form the mesa structure such that the growth surface of the first semiconducting layer comprises a mesa surface and a bulk semiconducting surface. Further, the monolithic LED structure is formed on the growth surface of the first semiconducting layer such that the monolithic LED structure covers the mesa surface and the bulk semiconducting surface, the monolithic LED structure comprising a plurality of layers, each layer comprising a Group III-nitride, including a second semiconducting layer, an active layer provided on the second semiconducting layer, the active layer configured to generate light, and a p-type semiconducting layer provided on the active layer. A potential barrier is provided between a first portion of the p-type semiconducting layer covering the mesa surface and a second portion of the p-type semiconducting layer covering the bulk semiconducting surface. The potential barrier surrounds the first portion of the p-type semiconducting layer covering the mesa surface.