Nitride Memory Cell With Segmented Charge Traps
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Solution Overview
Problem
Current non-volatile memory technologies, such as Flash memories with floating gate and charge trapping architectures, face challenges in scaling, programming time, data retention, and manufacturing costs, particularly due to issues like back-gate injection and silicon content affecting erasing performance and retention.
Innovation Solution
A memory cell system is developed with a first insulator layer, a charge trap layer, a second insulator layer, and a top and bottom blocking intermediate nitride layers to improve erase performance and data retention by reducing back-gate injection and boron penetration, while maintaining low manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon content in the nitride layer is increased to improve erasing performance, then erasing performance is improved, but data retention deteriorates
Solution Approach 1:
The patent divides the charge trapping function into two separate layers: a first charge trapping layer with high silicon content (60-100 at%) optimized for erasing performance, and a second charge trapping layer with low silicon content (0-40 at%) optimized for data retention. This segmentation allows each layer to specialize in one function without compromising the other, resolving the contradiction between erasing performance and data retention.
Solution Approach 2:
Different regions of the charge trapping structure are assigned different silicon concentrations tailored to their specific functional requirements. The first charge trapping layer uses high silicon content locally to enhance Fowler-Nordheim erase performance, while the second charge trapping layer uses low silicon content locally to improve data retention characteristics, allowing optimal performance in both aspects simultaneously.
2Reliability
If Fowler-Nordheim erase operation is used to improve erase performance, then erase performance is improved, but back-gate injection occurs causing charge loss
Solution Approach 1:
The patent introduces a blocking intermediate layer positioned between the charge trapping layers and the gate. This intermediary layer acts as a barrier that prevents electrons from tunneling from the gate into the charge trapping layers during Fowler-Nordheim erase operations, thereby eliminating back-gate injection and preventing charge loss while maintaining effective erase performance.
3Quantity of substance
If new semiconductor processes are used to scale Flash memories, then density is improved, but programming time increases and data retention decreases
Solution Approach 1:
The patent segments the charge trapping functionality into two distinct layers with different compositions and characteristics. The first charge trapping layer with high silicon content facilitates faster programming through efficient charge trapping, while the second charge trapping layer with low silicon content ensures long-term data retention. This segmentation enables the memory to maintain high density through scaling while preserving both programming speed and data retention characteristics.
4Device complexity
If a single nitride layer is used to simplify structure, then device complexity is reduced, but both erasing performance and data retention cannot be optimized simultaneously
Solution Approach 1:
Rather than using a single nitride layer, the patent segments the charge trapping function into two layers with different silicon contents. This segmentation, while increasing structural complexity, enables simultaneous optimization of both erasing performance (achieved by the high silicon content layer) and data retention (achieved by the low silicon content layer), resolving the contradiction between structural simplicity and functional performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances erase speed and data retention by reducing back-gate injection and cycled charge loss, while minimizing the equivalent oxide thickness and eliminating costly high-temperature processing steps, thus improving overall memory system efficiency and cost-effectiveness.
Implementation Method 1
Fowler-Nordheim electron tunneling is a desirable method for erase operation over hole direct tunneling which requires a very thin tunnel oxide, causing poor data retention.
Implementation Method 2
During Fowler-Nordheim erase operation, electrons can also tunnel from gate into the charge trapping layer through the top oxide. This phenomenon is often called back-gate injection.
Data Source
AI summary
A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.