Semiconductor Memory Nitride Layer Etching Protection
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Solution Overview
Problem
Existing semiconductor memory cells with multilayer memory elements on both side surfaces of a transistor gate electrode face issues with misalignment during the anisotropic etching process, which can damage the memory elements and require additional space to prevent damage, increasing size and cost.
Innovation Solution
A semiconductor memory structure featuring a gate electrode with a first silicon oxide layer, a charge trapping nitride layer, a second silicon oxide layer, and a protective silicon nitride layer, where the nitride layer has a rectangular cross-section and protects the memory elements during etching, allowing for precise alignment without increasing the memory cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick outer silicon nitride layer is added to protect memory elements during etching, then reliability improves, but memory cell size increases
Solution Approach 1:
The protective structure is divided into multiple thin silicon nitride layers (first and second protective layers) separated by a silicon oxide layer, rather than using a single thick nitride layer. This segmented approach provides sufficient etching protection while maintaining a compact footprint that does not increase memory cell area.
Solution Approach 2:
The protective structure combines multiple materials (silicon nitride and silicon oxide) in a composite multilayer configuration. The alternating nitride-oxide-nitride structure leverages the high etch resistance of nitride layers while using the oxide layer to reduce overall thickness and enable better space utilization within the memory cell.
2Reliability
If alignment margin space is increased to prevent etching damage, then reliability improves, but manufacturing precision requirements worsen
Solution Approach 1:
The multilayer protective structure is designed in advance to compensate for potential misalignment issues. The multiple thin nitride layers with intervening oxide layers create a cushioning effect that tolerates alignment variations during contact hole formation, preventing etching damage even when perfect alignment is not achieved.
3Area of stationary object
If the protective silicon nitride layer is made thinner to reduce area, then memory cell size decreases, but protection capability worsens
Solution Approach 1:
Instead of reducing the thickness of a single protective layer, the solution segments the protection into multiple thin nitride layers. The cumulative etch resistance of multiple thin layers equals or exceeds that of a single thick layer, while the segmented structure occupies less vertical and lateral space.
Solution Approach 2:
The composite nitride-oxide-nitride structure provides enhanced protection per unit thickness compared to a single material layer. The alternating layers create multiple barriers to etching while the oxide spacers reduce the overall footprint, achieving better protection-to-area ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures reliable and compact two-bit memory cells by preventing etching damage and allowing for higher alignment tolerance, maintaining performance comparable to conventional structures while reducing memory cell size and fabrication costs.
Implementation Method 1
These memories are programmed by hot electron injection from the channel beneath the gate into the trapping layer
Implementation Method 2
Contact holes are formed in the interlayer dielectric film by an anisotropic etching process to provide electrical access to the source and drain areas
Data Source
AI summary
A semiconductor memory has a gate electrode and a pair of multilayer memory elements formed on side surfaces of the gate electrode. Each multilayer memory element includes, in sequence from the gate electrode outward, a first silicon oxide layer, a charge trapping silicon nitride layer, a second silicon oxide layer, all with L-shaped cross sections, and a protective silicon nitride layer with an approximately rectangular cross section seated in the L-shape of the second silicon oxide layer. The protective silicon nitride layer protects the charge trapping silicon nitride layer from etching damage during the formation of contact holes without adding to the area occupied by the memory cell.