Nitride Planarization for Uniform Gate Heights
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Solution Overview
Problem
As integrated circuit structures scale down, non-planar nitride surfaces and nitride fins between p-type and n-type FET regions lead to uneven gate heights, causing non-uniformity and performance issues.
Innovation Solution
A method involving the formation of a dielectric layer over nitride layers with nitride fins, planarizing the dielectric to expose the nitride fins, and then forming a second nitride layer to achieve uniformity, followed by an etch to ensure the nitride layers are planar across all regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a nitride cap layer is formed over gate structures, then gate protection and isolation are improved, but nitride fins and bumps are formed causing non-planar surfaces and non-uniform gate heights
Solution Approach 1:
The patent removes the harmful nitride fins and bumps from the gate structure by selectively etching them away, while retaining the beneficial nitride cap layer for gate protection. This extraction of the defective portions resolves the contradiction between having gate protection and maintaining uniform gate heights.
Solution Approach 2:
The patent performs preliminary planarization steps before final gate formation to ensure a uniform surface. By pre-removing the nitride fins and bumps before subsequent processing steps, the method prevents gate height non-uniformity from developing in the first place.
2Ease of manufacture
If lithography is used to define PFET and NFET regions, then device region definition is improved, but nitride fins are formed between adjacent regions causing surface non-planarity
Solution Approach 1:
The patent selectively removes the nitride fins that form between adjacent PFET and NFET regions during lithography, extracting only the harmful portions while preserving the properly defined device regions. This maintains both easy device region definition and surface planarity.
Solution Approach 2:
The patent applies selective etching that targets only specific locations where nitride fins form between device regions, while leaving the nitride cap layer intact over the actual device regions. This localized treatment preserves surface planarity without affecting device region definition.
3Ease of manufacture
If nitride fins are present between PFET and NFET regions, then lithography patterning is simplified, but gate height uniformity and device performance deteriorate
Solution Approach 1:
The patent removes the nitride fins that are formed during simplified lithography patterning, extracting the harmful elements that cause gate height non-uniformity while preserving the benefit of simplified patterning processes.
Solution Approach 2:
The patent performs preliminary removal of nitride fins before subsequent gate formation steps, ensuring that gate height uniformity is established early in the process while maintaining the simplicity of the lithography patterning step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures uniform gate heights between p-type and n-type FET regions, improving device performance by eliminating nitride fins and bumps, thereby preventing gate height loss and ensuring consistent gate structure.
Implementation Method 1
planarizing the dielectric to a top surface of the set of nitride fins in the first region and removing the dielectric from the second region to expose the substantially planar upper surface in the second region
Implementation Method 2
planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins
Implementation Method 3
performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region
Data Source
AI summary
The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.