Nitride Semiconductor Plating Substrate Warpage Control
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Solution Overview
Problem
The fabrication of nitride semiconductor devices on sapphire substrates is hindered by warpage distortion and low thermal conductivity, making it difficult to produce vertical semiconductor devices and high-power light emitting elements with mass productivity.
Innovation Solution
A semiconductor light emitting element fabrication method using a plating substrate with a seed layer and plating layer made of materials like Ni, Cu, or Au, where spaces are formed in the plating layer between elements to reduce warpage and simplify the dicing process, eliminating the need for pre-forming grooves and removing sacrificial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal plating is used to form a support substrate on a nitride semiconductor layer, then thermal conductivity and electrical conductivity are improved, but warpage distortion occurs due to stress in the metal plating
Solution Approach 1:
The patent divides the continuous metal plating layer into segmented regions by forming insulating layers that create spaces between adjacent nitride semiconductor elements. This segmentation releases the stress accumulated in the metal plating, preventing warpage distortion while maintaining the thermal and electrical conductivity benefits of the metal support substrate.
Solution Approach 2:
The patent applies different properties to different regions of the support substrate: metal plating is applied in specific regions to provide thermal and electrical conductivity, while insulating layers are applied in other regions to create spaces that relieve stress. This local differentiation allows the system to simultaneously achieve conductivity and shape stability.
2Shape
If grooves are pre-formed on the growth substrate to separate nitride semiconductor layers, then warpage effects are reduced, but the fabrication process becomes complex requiring filling and removal of sacrificial layers
Solution Approach 1:
Instead of pre-forming grooves on the growth substrate before metal plating (the conventional approach), the patent inverts the sequence by first forming the metal plating layer continuously, then creating spaces in the metal plating by forming insulating layers. This reversal simplifies the process by eliminating the need for groove formation, sacrificial layer filling, and sacrificial layer removal.
Solution Approach 2:
The patent performs the space-forming action preliminarily during the metal plating process itself by using insulating layers as masks, rather than waiting until after the metal plating is complete. This preliminary formation of spaces prevents warpage from the outset and eliminates subsequent processing steps.
3Reliability
If a continuous metal plating layer is formed over the entire nitride semiconductor layer, then thermal and electrical conductivity are maximized, but dicing becomes difficult and warpage increases
Solution Approach 1:
The patent segments the continuous metal plating layer by introducing insulating layers that create spaces between adjacent elements. This segmentation provides natural separation lines that facilitate dicing while maintaining electrical conductivity within each individual element region. The metal plating remains continuous within each element but is electrically isolated from adjacent elements.
Solution Approach 2:
The patent creates local differences in the support substrate structure: continuous metal plating regions provide electrical conductivity within elements, while insulating layer regions provide separation for easy dicing. This local quality differentiation simultaneously achieves both electrical conductivity and ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces warpage distortion and improves mass production by releasing stress through the formed spaces, allowing for easier cutting and maintaining the integrity of the nitride semiconductor layer and plating substrate, enhancing the fabrication process and product quality.
Implementation Method 1
forming a plating layer on the seed layer; forming the plating substrate by removing the insulating layer and forming a space partially in the plating layer
Data Source
AI summary
A method of fabricating a plurality of light emitting elements includes forming a nitride semiconductor layer on a growth substrate, the nitride semiconductor layer including at least an n-type nitride semiconductor layer, an active layer made of a nitride semiconductor, and a p-type nitride semiconductor layer stacked in this order; forming a p-electrode layer, the p-electrode layer including portions that correspond to the light emitting elements; forming a p-passivation layer that includes portions between the portions of the p-electrode layer formed on the upper surface of the nitride semiconductor layer; forming a seed layer on the p-electrode layer and the p-passivation layer; forming an insulating layer having portions formed on an upper surface of the seed layer; forming a plating layer on the seed layer; and forming a plating substrate by removing the insulating layer to form spaces between portions of the plating layer.