Nitride Removal Protecting Shallow Junctions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As MOSFETs are scaled down, process variations in forming shallow source/drain junctions lead to increased dopant loss and variability in doping profiles, particularly at junction depths below 40 nm, causing issues with transistor performance and reliability.
Innovation Solution
The method involves forming a thin protective dielectric layer underneath a silicon nitride layer in the LDD or S/D regions, which minimizes or eliminates etching of the semiconductor surface, using a disposable nitride spacer to reduce dopant loss during implantation and nitride removal, and employing selective etching techniques to protect the surface from damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to remove silicon nitride, then the nitride layer is effectively removed, but significant dopant loss and surface damage occur in shallow junctions
Solution Approach 1:
A protective dielectric layer is formed on the semiconductor surface before ion implantation to prevent dopant loss during subsequent nitride removal etching processes. This preliminary protective action ensures that the surface is prepared in advance to withstand the harmful effects of conventional etching.
Solution Approach 2:
A silicon oxide protective layer is introduced as an intermediary between the silicon nitride layer and the silicon surface. This intermediary layer allows selective removal of the nitride while protecting the underlying silicon and implanted dopants from etching damage.
2Productivity
If MOSFET dimensions are scaled down to increase device density, then more devices fit per chip area, but process variations and dopant placement control become more erratic
Solution Approach 1:
The protective dielectric layer is formed prior to ion implantation to establish a stable foundation that prevents process-induced variations. This preliminary action compensates for the reduced margin of error in scaled devices by preventing dopant loss that would otherwise be magnified at smaller dimensions.
Solution Approach 2:
The invention changes the physical and chemical parameters of the surface by forming a protective oxide layer, which alters the etching characteristics and prevents dopant loss. This parameter change stabilizes the doping profile against process variations that become more significant at smaller device dimensions.
3Ease of manufacture
If screen dielectric thickness varies, then local and die-to-die variations in S/D junction profiles increase
Solution Approach 1:
The protective dielectric layer serves as an intermediary that decouples the variability in screen dielectric thickness from the final junction profile. By providing a consistent protective barrier, it compensates for upstream process variations and ensures uniform dopant retention across different locations and dies.
4Manufacturing precision
If silicon surface is etched after S/D implantation, then nitride removal is achieved, but significant dopant loss occurs leading to variation in doping profiles
Solution Approach 1:
A silicon oxide protective layer is introduced as an intermediary barrier between the etching process and the silicon surface. This intermediary layer is selectively removed after protecting the surface during nitride removal, ensuring complete nitride elimination while preserving the implanted dopants and maintaining doping profile consistency.
Solution Approach 2:
The harmful etching action is extracted and directed specifically at the silicon nitride layer while the protective oxide prevents the etchant from reaching the silicon surface and implanted dopants. This selective extraction of the harmful effect allows nitride removal without the associated dopant loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces process-induced variations in S/D doping profiles, minimizing dopant loss and surface roughening, thereby enhancing the consistency and reliability of transistor characteristics across IC dies.
Implementation Method 1
The method comprises selectively etching the silicon nitride layer using phosphoric acid
Implementation Method 2
forming a thin protective dielectric layer underneath a silicon nitride layer in the LDD or S/D regions, which minimizes or eliminates etching of the semiconductor surface
Implementation Method 3
ion implantation
Data Source
AI summary
A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.