Nitride ROM Retention via High Temperature Baking
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Solution Overview
Problem
Nitride read-only memory devices face challenges with charge retention due to charge loss and uneven eraseability, leading to poor endurance and increased difficulty in maintaining target threshold voltage windows, especially after program and erase cycles.
Innovation Solution
A retention improvement procedure involving a baking process in a high temperature environment to expel shallow trapped charges, followed by verification and reprogramming to ensure memory cells are in a high-Vt state, improving retention reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If band-to-band tunneling hot hole injection is used to erase cells, then erase capability is achieved, but oxide damage occurs leading to charge loss and reduced reliability
Solution Approach 1:
The patent applies high temperature baking to deliberately induce controlled charge loss from shallow trapping sites, converting the harmful effect of charge loss into a beneficial process that removes unstable charges and improves overall retention reliability
Solution Approach 2:
The patent changes the temperature parameter by applying high temperature baking (e.g., 150°C for 1 hour) to modify the charge distribution in the dielectric layer, expelling shallow trapped charges and stabilizing the threshold voltage distribution
2Ease of operation
If program and erase cycling is performed, then memory functionality is demonstrated, but charge accumulation occurs making subsequent erasure more difficult and closing the Vt window
Solution Approach 1:
The patent applies high temperature baking as a preliminary action before or after cycling to proactively remove accumulated shallow trapped charges, preventing them from interfering with subsequent erase operations and maintaining the Vt window
Solution Approach 2:
The patent converts the harmful charge accumulation effect into a beneficial process by using high temperature baking to selectively remove unstable shallow trapped charges, thereby improving eraseability and maintaining reliability after cycling
3Productivity
If sector erase is performed on nitride read-only memory, then data erasure is achieved, but process variations cause uneven erase speed and large Vt distribution
Solution Approach 1:
The patent applies high temperature baking to change the thermal energy parameter, which equalizes the charge distribution across cells with different threshold voltages, reducing the Vt distribution caused by process variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The procedure effectively enhances retention characteristics by reducing charge loss and improving the reliability of memory devices, both for uncycled and cycled cells, by ensuring deeper trapped charges are retained, thereby maintaining better performance over time.
Implementation Method 1
baking the plurality of memory cells at a temperature level for a sufficient duration to cause shallow trapped charges to be expelled from the plurality of memory cells
Data Source
AI summary
Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells, and a reprogramming process to program the memory device once again by programming memory cells in a 0-state to a high-Vt state. The baking step of placing the memory device in a high temperature environment causes a charge loss by expelling shallow trapped charges, resulting in the improvement of retention reliability.