Nitride Semiconductor Amorphous Regions for Low Parasitic Resistance
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Solution Overview
Problem
Existing semiconductor devices with nitride semiconductor layers face high parasitic resistance issues, which hinder the achievement of low loss and high withstanding voltage despite advancements in device miniaturization and material properties.
Innovation Solution
The formation of amorphous regions on the surface layers of impurity regions in nitride semiconductor devices, allowing for ohmic contact with metallic layers, reduces contact resistance and parasitic resistance, and enables low-temperature annealing processes suitable for large substrate sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing is performed to activate impurity regions and reduce parasitic resistance, then contact resistance decreases, but substrate damage occurs and manufacturing complexity increases
Solution Approach 1:
The patent changes the temperature parameter of the annealing process from high temperature (conventional) to low temperature (700-900°C), achieving activation of impurity regions and reduction of contact resistance without damaging the substrate. This parameter change resolves the contradiction by finding an optimal temperature window that provides sufficient thermal energy for impurity activation while remaining below the substrate's damage threshold.
Solution Approach 2:
The patent forms amorphous silicon regions that serve as intermediate contact layers between the metallic layers and the nitride semiconductor. These amorphous regions copy the beneficial effects of high-temperature annealing (impurity activation, resistance reduction) without requiring the damaging high-temperature process, effectively copying the desired outcome while avoiding the harmful process conditions.
2Reliability
If high-temperature annealing is performed to reduce parasitic resistance, then electrical conductivity improves, but substrate withstanding capability is exceeded
Solution Approach 1:
The patent modifies the temperature parameter from conventional high temperature to a reduced range of 700-900°C, which is sufficient to activate impurities and improve electrical conductivity through amorphous region formation, while staying within the substrate's thermal withstand capability. This parameter optimization resolves the contradiction between achieving good electrical conductivity and protecting the substrate from thermal damage.
3Reliability
If conventional high-temperature annealing is used to form ohmic contacts, then contact quality improves, but manufacturing cost increases due to process complexity
Solution Approach 1:
The patent reduces the annealing temperature parameter to 700-900°C, which simplifies the manufacturing process by eliminating the need for complex high-temperature equipment and process control systems while still achieving high-quality ohmic contacts through amorphous region formation. This parameter reduction directly lowers manufacturing costs while maintaining contact quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases parasitic resistance, achieving low loss and high withstanding voltage while simplifying the manufacturing process and reducing costs by allowing the use of substrates that cannot withstand high-temperature annealing.
Implementation Method 1
a first amorphous region FA1 and a second amorphous region SA1 are formed on surface layers of respectively a source region SR1 and a drain region DR1... the source electrode SE1 and the drain electrode DE1 come into contact with the amorphous regions FA1 and SA1 respectively
Implementation Method 2
annealing the semiconductor substrate... a first amorphous region FA1 and a second amorphous region SA1 are formed on surface layers of respectively a source region SR1 and a drain region DR1
Data Source
AI summary
A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region).