Nitride Semiconductor Apparatus Common Electrode Wiring

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Solution Overview

Problem

Conventional nitride semiconductor apparatuses experience parasitic inductance issues in electrode wiring between transistors and diodes, which hinder high-speed and low-loss operations, especially in step-up and step-down circuits.

Innovation Solution

The semiconductor apparatus features a nitride semiconductor layer with a transistor and diode configuration where the drain electrode of the transistor and the anode electrode of the diode are connected via a common electrode wiring, minimizing parasitic inductance by ensuring the shortest possible connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the transistor and diode are connected with shared drain electrode pad and anode electrode pad in conventional planar structure, then the device integration is achieved, but parasitic inductance is inevitably generated in electrode wiring

Engineering Contradiction:
Improvedevice integrationVSAvoidparasitic inductance
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent transitions from a planar two-dimensional layout to a three-dimensional vertical structure. The transistor and diode are stacked vertically with the transistor formed over the diode, allowing the drain electrode of the transistor to be directly connected to the anode electrode of the diode through vertical vias and common electrode wiring layers, thereby reducing parasitic inductance while maintaining integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges the drain electrode structure of the transistor with the anode electrode structure of the diode by forming them in the same horizontal position and connecting them through common electrode wiring layers. This merging eliminates separate connection paths and reduces the loop area, thereby minimizing parasitic inductance.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If parasitic inductance in electrode wiring is reduced for high-speed operation, then switching speed is improved, but electrode wiring complexity increases

Engineering Contradiction:
Improveswitching speedVSAvoidelectrode wiring complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent uses vertical stacking to reduce the horizontal distance between transistor drain and diode anode connections. By moving connections to the vertical dimension through vias and stacked layers, the patent achieves shorter current paths and lower parasitic inductance without requiring complex lateral wiring routes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The common electrode wiring layers serve multiple functions: they act as the drain electrode for the transistor, the anode electrode for the diode, and provide electrical connection between these two components. This multi-functionality reduces the need for separate dedicated connection structures, simplifying the overall wiring while achieving low parasitic inductance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly reduces parasitic inductance between the transistor and diode, enabling higher-speed and lower-loss operations in power factor correction circuits.

Implementation Method 1

high-concentration and high-mobility carriers are generated in a heterojunction interface due to spontaneous polarization and piezoelectric polarization without impurity doping

Methodology Applied
Scientific EffectSpontaneous polarization: Polarisation

Implementation Method 2

high-concentration and high-mobility carriers are generated in a heterojunction interface due to spontaneous polarization and piezoelectric polarization without impurity doping

Methodology Applied
Scientific EffectPiezoelectric polarization: Piezoelectric Effect

Data Source

PatentUS9484342B2Semiconductor apparatus
Publication Date: 2016.11.01 PANASONIC HOLDINGS CORP
  • US9484342B2 patent drawing
  • US9484342B2 patent drawing
  • US9484342B2 patent drawing

AI summary

A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.