Nitride Semiconductor Device With Doped Third Layer
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Solution Overview
Problem
Power semiconductor devices using silicon face limitations in breakdown voltage and on-resistance, while nitride semiconductor devices, especially normally-off type FETs, suffer from slower switching speed and increased on-resistance, making it difficult to achieve a desired threshold voltage.
Innovation Solution
A nitride semiconductor device with a third semiconductor layer made of gallium nitride containing a higher concentration of acceptor-type impurities is introduced between the first and second semiconductor layers, allowing for adjustment of the interface potential to achieve a desired normally-off operation with a high threshold voltage, preventing neutral regions and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a nitride semiconductor device uses a normally-off type FET configuration, then the number of components is reduced, but the switching speed decreases and on-resistance increases
Solution Approach 1:
The patent applies local quality by creating a third semiconductor layer with specifically doped regions (n-type and p-type) at different locations within the device structure. The n-type doped region is positioned in the channel formation region while the p-type doped region is positioned in the buffer layer, creating localized electrical properties that optimize both switching speed and threshold voltage control without requiring additional external components.
Solution Approach 2:
The patent introduces a vertical dimension to the device structure by stacking multiple semiconductor layers with different doping types and characteristics. The third semiconductor layer is positioned between the first and second semiconductor layers, creating a multi-layer vertical architecture that enables complex electrical behavior (normally-off operation with high switching speed) within a compact structure, avoiding the need for additional external components while maintaining performance.
2Device complexity
If a nitride semiconductor device uses a normally-off type FET configuration, then the number of components is reduced, but the on-resistance increases
Solution Approach 1:
The patent applies local quality by creating a third semiconductor layer with specifically doped regions (n-type and p-type) at different locations within the device structure. The n-type doped region is positioned in the channel formation region while the p-type doped region is positioned in the buffer layer, creating localized electrical properties that optimize both switching speed and threshold voltage control without requiring additional external components.
Solution Approach 2:
The patent introduces a vertical dimension to the device structure by stacking multiple semiconductor layers with different doping types and characteristics. The third semiconductor layer is positioned between the first and second semiconductor layers, creating a multi-layer vertical architecture that enables complex electrical behavior (normally-off operation with high switching speed) within a compact structure, avoiding the need for additional external components while maintaining performance.
3Device complexity
If a nitride semiconductor device uses a normally-off type FET configuration, then the number of components is reduced, but the threshold voltage control becomes difficult
Solution Approach 1:
The patent applies local quality by creating a third semiconductor layer with specifically doped regions (n-type and p-type) at different locations within the device structure. The n-type doped region is positioned in the channel formation region while the p-type doped region is positioned in the buffer layer, creating localized electrical properties that optimize both switching speed and threshold voltage control without requiring additional external components.
Solution Approach 2:
The patent introduces a vertical dimension to the device structure by stacking multiple semiconductor layers with different doping types and characteristics. The third semiconductor layer is positioned between the first and second semiconductor layers, creating a multi-layer vertical architecture that enables complex electrical behavior (normally-off operation with high switching speed) within a compact structure, avoiding the need for additional external components while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a nitride semiconductor device with a high switching speed and desired positive threshold voltage, reducing on-resistance and enhancing breakdown voltage, thus overcoming the limitations of silicon-based devices and improving the performance of normally-off type FETs.
Implementation Method 1
a third semiconductor layer made of gallium nitride containing a higher concentration of acceptor-type impurities than each of the first and second semiconductor layers
Data Source
AI summary
A nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer including a nitride semiconductor provided between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer being contact with the first semiconductor layer and the second semiconductor layer, and a concentration of acceptor type impurity in the third semiconductor layer is higher than that in the first semiconductor layer and the second semiconductor layer, and including a source electrode and a drain electrode, a gate electrode, a first insulating layer, and a fourth semiconductor layer and a fifth semiconductor layer, wherein the nitride semiconductor device satisfying the following formula 0<d<2[(2∈Eg)/(qNa)]1/2.