Nitride Semiconductor Device with Low Carrier Drain Layer
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Solution Overview
Problem
The existing semiconductor device structure, which uses p-GaN for both the gate and drain electrode sides, faces challenges in achieving normally-OFF operation while maintaining low ON resistance, as thinning the AlGaN barrier layer under the gate depletes the 2DEG channel, leading to current collapse and increased process complexity.
Innovation Solution
Incorporating a fourth nitride semiconductor layer with a lower average carrier concentration between the third nitride semiconductor layer (acting as the gate) and the drain electrode, allowing for normally-OFF operation without the need for a recess under the gate, thereby simplifying the process and reducing ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the AlGaN barrier layer is thinned under the gate to deplete the 2DEG channel for normally-OFF operation, then the gate control is improved, but the ON resistance increases and current collapse occurs
Solution Approach 1:
The patent applies local quality by creating a recess structure only under the gate electrode, while maintaining the full thickness of the AlGaN barrier layer in other regions. This localized thinning allows the 2DEG channel to be depleted under the gate for normally-OFF operation, while preserving low ON resistance in the source and drain regions where the barrier layer remains thick.
Solution Approach 2:
The patent segments the AlGaN barrier layer into two distinct regions: a thinned region under the gate and a full-thickness region in the source and drain areas. This segmentation enables different functional requirements to be met in different locations - depletion under the gate for normally-OFF operation and maintained conductivity in the source/drain regions for low ON resistance.
2Reliability
If the AlGaN barrier layer is thinned under the gate for normally-OFF operation, then the gate control is improved, but the process complexity increases due to required epitaxial regrowth
Solution Approach 1:
The patent employs preliminary action by forming the recess structure under the gate electrode before completing the epitaxial growth of the AlGaN barrier layer. This allows the recess to be created as a physical template that guides subsequent material deposition, eliminating the need for complex post-growth processing steps such as selective removal or regrowth.
Solution Approach 2:
The recess structure serves as an intermediary element that facilitates the formation of the normally-OFF structure. By creating this physical cavity before epitaxial growth, the recess acts as a mold or template that automatically defines the thinned region, simplifying the overall manufacturing process compared to attempting to create the same structure through complex selective etching or regrowth techniques.
3Device complexity
If p-GaN is used for both gate and drain electrode sides, then the structure is simplified, but current collapse occurs due to electron trapping
Solution Approach 1:
The patent applies local quality by differentiating the treatment of p-GaN layers under the gate versus under the drain electrode. The recess structure is created only under the gate, creating a localized region with different electrical characteristics. This allows the device to achieve normally-OFF operation under the gate while maintaining current collapse suppression under the drain through the presence of the p-GaN layer in its original configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables easy realization of normally-OFF operation with low ON resistance, reduces current collapse, and minimizes the need for epitaxial regrowth, resulting in simpler and cost-effective manufacturing processes while maintaining high-speed operation.
Implementation Method 1
can generate an electron channel (two-dimensional electron gas 2 DEG) with high mobility and a high concentration on a GaN layer side of an AlGaN/GaN interface due to piezo charges generated from a lattice constant difference between an AlGaN barrier layer and a GaN channel layer
Implementation Method 2
a p-type group-III nitride semiconductor is provided between a gate electrode and the AlGaN barrier layer, thereby forming a p-n junction under a gate and depleting only the 2 DEG channel located under the gate
Data Source
AI summary
A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer having a greater band gap than the first nitride semiconductor layer; a source electrode and a drain electrode on the second nitride semiconductor layer apart from each other; a third nitride semiconductor layer, between the source electrode and the drain electrode, containing a p-type first impurity and serving as a gate; and a fourth nitride semiconductor layer, between the third nitride semiconductor layer and the drain electrode, containing a p-type second impurity, wherein the average carrier concentration of the fourth nitride semiconductor layer is lower than the average carrier concentration of the third nitride semiconductor layer.