Nitride Semiconductor Device Gate Capacitance Reduction
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Solution Overview
Problem
Nitride semiconductor devices face issues with high parasitic capacitance and current collapse due to the active 2DEG layer outside the gate recess, which hinders high-speed driving and reduces drain current when a high drain voltage is applied.
Innovation Solution
A nitride semiconductor device configuration with a p-type nitride semiconductor layer partially disposed inside a recess, separated from the recess side surface, and a layered structure with varying band gaps to increase the distance between the 2DEG layer and the p-type layer, reducing parasitic capacitance and inhibiting current collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick barrier layer is made in regions other than the gate recess to dispose the nitride semiconductor layer far from the 2DEG layer, then current collapse is inhibited, but parasitic capacitance between the p-type semiconductor layer and the 2DEG layer increases
Solution Approach 1:
The patent applies local quality by creating different barrier layer thicknesses in different regions: a thick barrier layer in the gate recess region to inhibit current collapse, and a thin or absent barrier layer in regions outside the gate recess to reduce parasitic capacitance. This spatial differentiation of barrier layer properties resolves the contradiction between reliability and harmful factors.
Solution Approach 2:
The barrier layer is segmented into different thickness regions corresponding to the gate recess area and the surrounding areas. The gate recess region maintains a thick barrier layer while the outer regions have reduced barrier layer thickness, allowing independent optimization of current collapse inhibition and parasitic capacitance reduction.
2Reliability
If the p-type semiconductor layer covers the gate recess to inhibit current collapse, then device reliability improves, but gate capacitance increases hindering high-speed driving
Solution Approach 1:
The p-type semiconductor layer is selectively positioned only in the gate recess region rather than covering the entire surface. This local placement maintains the benefit of current collapse inhibition in the critical gate area while minimizing the parasitic capacitance that would result from extensive p-type layer coverage, thereby preserving high-speed driving capability.
Solution Approach 2:
The p-type semiconductor layer is extracted from the regions outside the gate recess, leaving only the essential gate recess area covered. This removal of unnecessary p-type material reduces parasitic capacitance and improves switching speed while maintaining sufficient coverage for current collapse inhibition.
Data Source
AI summary
A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.