Nitride Semiconductor Interconnects for Low On-Resistance
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Solution Overview
Problem
Conventional nitride semiconductor devices with large electrode pads face limitations in downsizing due to increased interconnect resistance when trying to reduce on-resistance and enhance maximum current per gate width, as increasing gate width leads to higher on-resistance and reduced voltage difference between source and gate electrodes.
Innovation Solution
The nitride semiconductor device incorporates an interconnect layer sandwiched between the electrode interconnect layer and the pad layer, with alternating first and second interconnect layers connected through insulating films, reducing interconnect length and increasing their apparent number to lower interconnection resistance, and using high-conductive metals with strong adhesion to insulating films to maintain conductivity and prevent peeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If electrode pads are made large to handle large current, then current handling capability is improved, but device size cannot be sufficiently downsized
Solution Approach 1:
The patent transitions from a planar pad layout to a three-dimensional stacked configuration. Multiple pad layers (first pad layer and second pad layer) are arranged vertically above the active region, separated by insulating films. This vertical stacking allows current paths to be distributed across multiple levels, effectively increasing current handling capability without expanding the lateral footprint of the device.
Solution Approach 2:
The patent implements a nested structure where pad layers are positioned within the vertical space above the active region. The first pad layer and second pad layer are nested at different heights, with each layer contributing to current distribution. This nesting approach maximizes the use of available three-dimensional space, allowing large effective pad area without increasing device footprint.
2Power
If gate width is increased to reduce on-resistance and increase maximum current, then current handling is improved, but interconnect resistance increases and voltage difference between source and gate decreases
Solution Approach 1:
The patent introduces vertical interconnect layers (first interconnect layer and second interconnect layer) stacked above the active region, connected through insulating films with openings. This three-dimensional interconnect structure reduces the lateral distance current must travel, thereby reducing interconnect resistance without requiring increased gate width. The vertical arrangement creates shorter current paths compared to traditional planar layouts.
Solution Approach 2:
The patent segments the current path into multiple vertical stages through alternating interconnect layers and insulating films. Instead of a single long lateral interconnect, the current travels through multiple shorter vertical segments. This segmentation reduces the total interconnect resistance by breaking up the current path into manageable sections with smaller resistance contributions.
3Area of stationary object
If pad-on-element structure is used to downsize devices, then device size is reduced, but thick interlayer films are required to prevent leakage current
Solution Approach 1:
The patent employs composite insulating film structures consisting of multiple layers with different functional properties. The interlayer films are composed of materials selected for both their insulating properties and their ability to prevent leakage current at reduced thicknesses. This composite approach allows thin film implementation while maintaining adequate electrical isolation between stacked pad layers.
Solution Approach 2:
The patent optimizes the thickness and material composition parameters of interlayer films to achieve adequate insulation at reduced thickness. By carefully selecting film materials and adjusting thickness parameters, the design prevents leakage current between pad layers while maintaining compact vertical dimensions, thus enabling downsizing without excessive film thickness.
Data Source
AI summary
A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings.