Nitride Semiconductor Device with Island-Like Cells
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Solution Overview
Problem
Conventional nitride semiconductor devices face challenges in reducing on-resistance and increasing maximum current per gate width due to increased interconnection resistance and voltage differences between source and gate electrodes, limiting their downsizing and high-power handling capabilities.
Innovation Solution
The nitride semiconductor device features electrodes divided into sections with interconnects and insulating films, forming island-like cells to reduce interconnection resistance and allow for smaller interconnect lengths, thereby decreasing on-resistance and preventing electron migration, while maintaining high current capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If electrode pads are formed above an active region (pad-on-element structure), then device downsizing is enabled, but on-resistance increases due to longer interconnection paths
Solution Approach 1:
The device is divided into multiple independent island-like cells, each with its own electrodes and interconnects. This segmentation allows current to flow through multiple parallel paths, reducing the effective on-resistance while maintaining a compact chip area. Each cell operates independently, and the collective effect of multiple cells achieves the desired current handling capability with lower resistance.
Solution Approach 2:
The patent transitions from a planar electrode arrangement to a three-dimensional structure by forming electrodes and interconnects at multiple vertical levels. This dimensional change allows current to flow through both horizontal and vertical paths, effectively reducing the interconnection resistance while maintaining a small footprint area.
2Power
If gate width is increased to handle larger current, then maximum current capability improves, but interconnection resistance increases causing higher on-resistance
Solution Approach 1:
Instead of using a single large gate, the device employs multiple smaller gates arranged in parallel across separate island cells. This segmentation maintains a large effective gate width for high current capability while keeping individual interconnection paths short, thereby minimizing on-resistance.
Solution Approach 2:
Multiple island cells are electrically merged through parallel connection of their respective electrodes and interconnects. This merging achieves the effect of a large gate width and high current capability while each cell contributes to reducing the total on-resistance through parallel current paths.
3Reliability
If interconnect length is reduced to decrease on-resistance, then device area decreases, but electron migration increases
Solution Approach 1:
The patent addresses electron migration by forming interconnects at multiple vertical levels rather than relying solely on long horizontal paths. This three-dimensional interconnection structure reduces the horizontal interconnect length (minimizing electron migration) while using vertical stacking to maintain electrical connectivity and current handling capability.
Solution Approach 2:
Different regions of the device have optimized local structures: island cells with compact interconnects minimize electron migration in critical areas, while the overall multi-cell arrangement maintains low on-resistance. The local quality of each cell is optimized for its specific function, with interconnect dimensions and materials tailored to prevent electron migration while achieving low resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces on-resistance and increases maximum current per gate width, enabling the device to handle larger currents and higher voltages with reduced chip area and minimized electron migration.
Implementation Method 1
hetero-junction field effect transistors (HFETs) utilizing two-dimensional electron gas (2DEG) produced at the interface between an aluminum gallium nitride (AlxGa1-xN, where 0<x<1) layer and a gallium nitride (GaN) layer
Implementation Method 2
Group III-V nitride semiconductors which are represented by the general formula: AlxGa1-x-yInyN, where 0≦x≦1, 0≦y≦1, and 0≦x+y≦1, have a wide band gap
Data Source
AI summary
A nitride semiconductor device includes: first electrode interconnect layers extending in parallel with one another over the nitride semiconductor layer and divided by areas extending across a longitudinal direction of the first electrode interconnect layers; first gate electrodes extending along the first electrode interconnect layers; first gate electrode connecting interconnects extending in associated ones of the areas dividing the first electrode interconnect layers and being in connection to the first gate electrodes; first electrode connecting interconnects formed above the first gate electrode connecting interconnects and being in connection to the first electrode interconnect layers; a first electrode upper interconnects formed on the first electrode connecting interconnects with an interconnect insulating film interposed therebetween, and being in connection to the first electrode connecting interconnects through associated ones of openings of the interconnect insulating film.