Nitride Semiconductor Device Reducing On-Resistance via Preliminary Layer Formation
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Solution Overview
Problem
Current methods for manufacturing nitride semiconductor MIS field effect transistors face challenges in achieving low on-resistance and stable operation due to issues with crystallinity, impurity concentration, and defect formation during epitaxial growth, particularly in the formation of the electron supply layer, which affects the two-dimensional electron gas and device yield.
Innovation Solution
The approach involves forming a nitride semiconductor device with a specific layer structure and etching process to control the gate region, using a second electron transit layer as a recess stopper to simplify the manufacturing process, ensure good crystallinity, and reduce on-resistance, while maintaining normally-off characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the electron supply layer is formed selectively only in regions other than the gate region through twice epitaxial growth, then the structure of the MIS field effect transistor can be formed precisely, but the manufacturing time increases significantly and production efficiency deteriorates
Solution Approach 1:
The electron supply layer is formed in advance across the entire semiconductor layer before the gate electrode is formed, rather than forming it selectively after the gate region is defined. This preliminary formation eliminates the need for a second epitaxial growth step and mask protection processes, significantly reducing manufacturing time while maintaining structural precision through subsequent selective removal in the gate region.
2Manufacturing precision
If the electron supply layer is formed selectively through twice epitaxial growth, then the structural precision can be improved, but the manufacturing process complexity increases due to mask protection requirements
Solution Approach 1:
The electron supply layer is formed in advance across the entire semiconductor layer before the gate electrode is formed, rather than forming it selectively after the gate region is defined. This preliminary formation eliminates the need for a second epitaxial growth step and mask protection processes, significantly reducing manufacturing time while maintaining structural precision through subsequent selective removal in the gate region.
3Manufacturing precision
If the electron supply layer is formed selectively through twice epitaxial growth, then the structural precision can be improved, but the crystallinity deteriorates due to re-growth interface defects
Solution Approach 1:
The electron supply layer is formed in advance across the entire semiconductor layer in a single continuous epitaxial growth process, eliminating re-growth interface defects that would deteriorate crystallinity and increase on-resistance. The layer is subsequently selectively removed in the gate region to achieve the desired structure without compromising the crystalline quality of the remaining layers.
4Manufacturing precision
If the electron supply layer is formed selectively through twice epitaxial growth, then the structural precision can be improved, but the on-resistance increases due to defect formation at re-growth interfaces
Solution Approach 1:
The electron supply layer is formed in advance across the entire semiconductor layer in a single continuous epitaxial growth process, eliminating re-growth interface defects that would deteriorate crystallinity and increase on-resistance. The layer is subsequently selectively removed in the gate region to achieve the desired structure without compromising the crystalline quality of the remaining layers.
5Manufacturing precision
If the electron supply layer is formed selectively through twice epitaxial growth, then the structural precision can be improved, but the device stability deteriorates due to impurity incorporation
Solution Approach 1:
The electron supply layer is formed in advance across the entire semiconductor layer in a single continuous epitaxial growth process, eliminating re-growth interface defects that would deteriorate crystallinity and increase on-resistance. The layer is subsequently selectively removed in the gate region to achieve the desired structure without compromising the crystalline quality of the remaining layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of nitride semiconductor devices with reduced on-resistance and improved stability, ensuring efficient mass production and maintaining the normally-off characteristics by controlling the etching depth and crystallinity, thus enhancing the device's electrical properties.
Implementation Method 1
due to a piezoelectric effect and depolarization, a two-dimensional electron gas is formed at a hetero interface between the electron supply layer 403 and the electron transit layer 402, which leads to a reduction in on resistance
Data Source
AI summary
Object of the invention is to reduce the on resistance between source and drain of a nitride semiconductor device. Between a nitride semiconductor layer lying between source and drain regions and a nitride semiconductor layer serving as an underlying layer, formed is a material having an electron affinity greater than that of these nitride semiconductor layers and having a lattice constant greater than that of the nitride semiconductor layer serving as an underlying layer. As a result, an electron density distribution of a channel formed below a gate insulating film and that of a two-dimensional electron gas formed in a region other than the gate portion, when a gate voltage is applied, can be made closer in the depth direction, leading to reduction in on resistance.